11 files changed, 39 insertions, 23 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index dd4698c67cc3..baf638487a2d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1,9 +1,5 @@
 comment "Processor Type"
 
-config CPU_32
-        bool
-        default y
-
 # Select CPU types depending on the architecture selected.  This selects
 # which CPUs we support in the kernel image, and the compiler instruction
 # optimiser behaviour.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 827e238e5d4a..e8d34a80851c 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -27,6 +27,9 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ)	+= abort-ev5tj.o
 obj-$(CONFIG_CPU_ABRT_EV6)      += abort-ev6.o
 obj-$(CONFIG_CPU_ABRT_EV7)      += abort-ev7.o
 
+AFLAGS_abort-ev6.o      :=-Wa,-march=armv6k
+AFLAGS_abort-ev7.o      :=-Wa,-march=armv7-a
+
 obj-$(CONFIG_CPU_PABRT_LEGACY)  += pabort-legacy.o
 obj-$(CONFIG_CPU_PABRT_V6)      += pabort-v6.o
 obj-$(CONFIG_CPU_PABRT_V7)      += pabort-v7.o
@@ -39,6 +42,9 @@ obj-$(CONFIG_CPU_CACHE_V6)	+= cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
 
+AFLAGS_cache-v6.o       :=-Wa,-march=armv6
+AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
+
 obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
 obj-$(CONFIG_CPU_COPY_V4WB)     += copypage-v4wb.o
@@ -58,6 +64,9 @@ obj-$(CONFIG_CPU_TLB_V6)	+= tlb-v6.o
 obj-$(CONFIG_CPU_TLB_V7)        += tlb-v7.o
 obj-$(CONFIG_CPU_TLB_FA)        += tlb-fa.o
 
+AFLAGS_tlb-v6.o         :=-Wa,-march=armv6
+AFLAGS_tlb-v7.o         :=-Wa,-march=armv7-a
+
 obj-$(CONFIG_CPU_ARM610)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM710)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM7TDMI)      += proc-arm7tdmi.o
@@ -84,6 +93,9 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
 
+AFLAGS_proc-v6.o        :=-Wa,-march=armv6
+AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
+
 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)      += cache-xsc3l2.o
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5d180cb0bd94..c3154928bccd 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void)
         if (!cpu_is_xsc3() || !xsc3_l2_present())
                 return 0;
 
-        if (!(get_cr() & CR_L2)) {
+        if (get_cr() & CR_L2) {
                 pr_info("XScale3 L2 cache enabled.\n");
-                adjust_cr(CR_L2, CR_L2);
                 xsc3_l2_inv_all();
-        }
 
-        outer_cache.inv_range = xsc3_l2_inv_range;
-        outer_cache.clean_range = xsc3_l2_clean_range;
-        outer_cache.flush_range = xsc3_l2_flush_range;
+                outer_cache.inv_range = xsc3_l2_inv_range;
+                outer_cache.clean_range = xsc3_l2_clean_range;
+                outer_cache.flush_range = xsc3_l2_flush_range;
+        }
 
         return 0;
 }
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 841f355319bf..0fa1319273de 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -48,7 +48,7 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
          */
         if (page_address(to) != NULL)
 #endif
-                __cpuc_flush_dcache_page(kto);
+                __cpuc_flush_dcache_area(kto, PAGE_SIZE);
         kunmap_atomic(kto, KM_USER1);
         kunmap_atomic(kfrom, KM_USER0);
 }
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 729602291958..56ee15321b00 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -207,9 +207,8 @@ void __init check_writebuffer_bugs(void)
         page = alloc_page(GFP_KERNEL);
         if (page) {
                 unsigned long *p1, *p2;
-                pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
-                                         L_PTE_DIRTY|L_PTE_WRITE|
-                                         L_PTE_MT_BUFFERABLE);
+                pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
+                                        L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
 
                 p1 = vmap(&page, 1, VM_IOREMAP, prot);
                 p2 = vmap(&page, 1, VM_IOREMAP, prot);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 52c40d155672..a04ffbbbe253 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -616,7 +616,7 @@ void __init mem_init(void)
                 "%dK data, %dK init, %luK highmem)\n",
                 nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10,
                 datasize >> 10, initsize >> 10,
-                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
+                totalhigh_pages << (PAGE_SHIFT-10));
 
         if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
                 extern int sysctl_overcommit_memory;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 8c7fbd19a4b3..761ffede6a23 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -453,8 +453,7 @@ static void __init build_mem_type_table(void)
 
         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
-                                 L_PTE_DIRTY | L_PTE_WRITE |
-                                 L_PTE_EXEC | kern_pgprot);
+                                 L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
 
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
@@ -1068,4 +1067,6 @@ void setup_mm_for_reboot(char mode)
                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
                 flush_pmd_entry(pmd);
         }
+
+        local_flush_tlb_all();
 }
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 395cc90c6613..7a5337ed7d68 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin)
  *      to what would be the reset vector.
  *
  *      - loc   - location to jump to for soft reset
- *
- *      It is assumed that:
  */
         .align  5
 ENTRY(cpu_v6_reset)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a285218fd15..7aaf88a3b7aa 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,7 +45,14 @@ ENTRY(cpu_v7_proc_init)
 ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
-        mov     pc, lr
+        stmfd   sp!, {lr}
+        cpsid   if                              @ disable interrupts
+        bl      v7_flush_kern_cache_all
+        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
+        bic     r0, r0, #0x1000                 @ ...i............
+        bic     r0, r0, #0x0006                 @ .............ca.
+        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
+        ldmfd   sp!, {pc}
 ENDPROC(cpu_v7_proc_fin)
 
 /*
@@ -56,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin)
  *      to what would be the reset vector.
  *
  *      - loc   - location to jump to for soft reset
- *
- *      It is assumed that:
  */
         .align  5
 ENTRY(cpu_v7_reset)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 96456f548798..8e4f6dca8997 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -407,6 +407,13 @@ __xsc3_setup:
 
         adr     r5, xsc3_crval
         ldmia   r5, {r5, r6}
+
+#ifdef CONFIG_CACHE_XSC3L2
+        mrc     p15, 1, r0, c0, c0, 1           @ get L2 present information
+        ands    r0, r0, #0xf8
+        orrne   r6, r6, #(1 << 26)              @ enable L2 if present
+#endif
+
         mrc     p15, 0, r0, c1, c0, 0           @ get control register
         bic     r0, r0, r5                      @ ..V. ..R. .... ..A.
         orr     r0, r0, r6                      @ ..VI Z..S .... .C.M (mmu)
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index a26a605b73bd..0cb1848bd876 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -40,7 +40,6 @@ ENTRY(v7wbi_flush_user_tlb_range)
         asid    r3, r3                          @ mask ASID
         orr     r0, r3, r0, lsl #PAGE_SHIFT     @ Create initial MVA
         mov     r1, r1, lsl #PAGE_SHIFT
-        vma_vm_flags r2, r2                     @ get vma->vm_flags
 1:
 #ifdef CONFIG_SMP
         mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable)