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-rw-r--r--arch/arm/mm/cache-v4wb.S2
-rw-r--r--arch/arm/mm/cache-v4wt.S2
-rw-r--r--arch/arm/mm/cache-v7.S2
-rw-r--r--arch/arm/mm/proc-arm1020.S2
-rw-r--r--arch/arm/mm/proc-arm1020e.S2
-rw-r--r--arch/arm/mm/proc-arm1022.S2
-rw-r--r--arch/arm/mm/proc-arm1026.S2
-rw-r--r--arch/arm/mm/proc-arm720.S2
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm922.S2
-rw-r--r--arch/arm/mm/proc-arm925.S2
-rw-r--r--arch/arm/mm/proc-macros.S2
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7.S2
14 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index d3644db467b7..f40c69656d8d 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -32,7 +32,7 @@
32/* 32/*
33 * This is the size at which it becomes more efficient to 33 * This is the size at which it becomes more efficient to
34 * clean the whole cache, rather than using the individual 34 * clean the whole cache, rather than using the individual
35 * cache line maintainence instructions. 35 * cache line maintenance instructions.
36 * 36 *
37 * Size Clean (ticks) Dirty (ticks) 37 * Size Clean (ticks) Dirty (ticks)
38 * 4096 21 20 21 53 55 54 38 * 4096 21 20 21 53 55 54
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 49c2b66cf3dd..a7b276dbda11 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -34,7 +34,7 @@
34/* 34/*
35 * This is the size at which it becomes more efficient to 35 * This is the size at which it becomes more efficient to
36 * clean the whole cache, rather than using the individual 36 * clean the whole cache, rather than using the individual
37 * cache line maintainence instructions. 37 * cache line maintenance instructions.
38 * 38 *
39 * *** This needs benchmarking 39 * *** This needs benchmarking
40 */ 40 */
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 6136e68ce953..dc18d81ef8ce 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all)
96 * Flush the entire cache system. 96 * Flush the entire cache system.
97 * The data cache flush is now achieved using atomic clean / invalidates 97 * The data cache flush is now achieved using atomic clean / invalidates
98 * working outwards from L1 cache. This is done using Set/Way based cache 98 * working outwards from L1 cache. This is done using Set/Way based cache
99 * maintainance instructions. 99 * maintenance instructions.
100 * The instruction cache can still be invalidated back to the point of 100 * The instruction cache can still be invalidated back to the point of
101 * unification in a single instruction. 101 * unification in a single instruction.
102 * 102 *
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 226e3d8351c2..6c4e7fd6c8af 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -64,7 +64,7 @@
64/* 64/*
65 * This is the size at which it becomes more efficient to 65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual 66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions. 67 * cache line maintenance instructions.
68 */ 68 */
69#define CACHE_DLIMIT 32768 69#define CACHE_DLIMIT 32768
70 70
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 86d9c2cf0bce..4ce947c19623 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -64,7 +64,7 @@
64/* 64/*
65 * This is the size at which it becomes more efficient to 65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual 66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions. 67 * cache line maintenance instructions.
68 */ 68 */
69#define CACHE_DLIMIT 32768 69#define CACHE_DLIMIT 32768
70 70
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 83d3dd34f846..c8884c5413a2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -53,7 +53,7 @@
53/* 53/*
54 * This is the size at which it becomes more efficient to 54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual 55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions. 56 * cache line maintenance instructions.
57 */ 57 */
58#define CACHE_DLIMIT 32768 58#define CACHE_DLIMIT 32768
59 59
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 686043ee7281..413684660aad 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -53,7 +53,7 @@
53/* 53/*
54 * This is the size at which it becomes more efficient to 54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual 55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions. 56 * cache line maintenance instructions.
57 */ 57 */
58#define CACHE_DLIMIT 32768 58#define CACHE_DLIMIT 32768
59 59
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 665266da143c..7a06e5964f59 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -63,7 +63,7 @@ ENTRY(cpu_arm720_proc_fin)
63/* 63/*
64 * Function: arm720_proc_do_idle(void) 64 * Function: arm720_proc_do_idle(void)
65 * Params : r0 = unused 65 * Params : r0 = unused
66 * Purpose : put the processer in proper idle mode 66 * Purpose : put the processor in proper idle mode
67 */ 67 */
68ENTRY(cpu_arm720_do_idle) 68ENTRY(cpu_arm720_do_idle)
69 mov pc, lr 69 mov pc, lr
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 219980ec8b6e..b46eb21f05c7 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -53,7 +53,7 @@
53/* 53/*
54 * This is the size at which it becomes more efficient to 54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual 55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions. 56 * cache line maintenance instructions.
57 */ 57 */
58#define CACHE_DLIMIT 65536 58#define CACHE_DLIMIT 65536
59 59
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 36154b1e792a..95ba1fc56e4d 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -54,7 +54,7 @@
54/* 54/*
55 * This is the size at which it becomes more efficient to 55 * This is the size at which it becomes more efficient to
56 * clean the whole cache, rather than using the individual 56 * clean the whole cache, rather than using the individual
57 * cache line maintainence instructions. (I think this should 57 * cache line maintenance instructions. (I think this should
58 * be 32768). 58 * be 32768).
59 */ 59 */
60#define CACHE_DLIMIT 8192 60#define CACHE_DLIMIT 8192
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 89c5e0009c4c..541e4774eea1 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -77,7 +77,7 @@
77/* 77/*
78 * This is the size at which it becomes more efficient to 78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual 79 * clean the whole cache, rather than using the individual
80 * cache line maintainence instructions. 80 * cache line maintenance instructions.
81 */ 81 */
82#define CACHE_DLIMIT 8192 82#define CACHE_DLIMIT 8192
83 83
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e32fa499194c..34261f9486b9 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -85,7 +85,7 @@
85 85
86/* 86/*
87 * Sanity check the PTE configuration for the code below - which makes 87 * Sanity check the PTE configuration for the code below - which makes
88 * certain assumptions about how these bits are layed out. 88 * certain assumptions about how these bits are laid out.
89 */ 89 */
90#ifdef CONFIG_MMU 90#ifdef CONFIG_MMU
91#if L_PTE_SHARED != PTE_EXT_SHARED 91#if L_PTE_SHARED != PTE_EXT_SHARED
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 832b6bdc192c..bfa0c9f611c5 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend)
132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
135 mrc p15, 0, r9, c1, c0, 1 @ auxillary control register 135 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control 136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
137 mrc p15, 0, r11, c1, c0, 0 @ control register 137 mrc p15, 0, r11, c1, c0, 0 @ control register
138 stmia r0, {r4 - r11} 138 stmia r0, {r4 - r11}
@@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume)
151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
154 mcr p15, 0, r9, c1, c0, 1 @ auxillary control register 154 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control 155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
157 mcr p15, 0, ip, c7, c5, 4 @ ISB 157 mcr p15, 0, ip, c7, c5, 4 @ ISB
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 262fa88a7439..c35618e42f6f 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -237,7 +237,7 @@ ENTRY(cpu_v7_do_resume)
237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
240 mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register 240 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
242 ldr r4, =PRRR @ PRRR 242 ldr r4, =PRRR @ PRRR
243 ldr r5, =NMRR @ NMRR 243 ldr r5, =NMRR @ NMRR
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 12:54:59 -0500