diff options
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/Makefile | 12 | ||||
-rw-r--r-- | arch/arm/mm/alignment.c | 3 | ||||
-rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 11 | ||||
-rw-r--r-- | arch/arm/mm/init.c | 2 | ||||
-rw-r--r-- | arch/arm/mm/mmu.c | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm6_7.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 11 | ||||
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 7 | ||||
-rw-r--r-- | arch/arm/mm/tlb-v7.S | 1 |
10 files changed, 39 insertions, 14 deletions
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 827e238e5d4a..e8d34a80851c 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile | |||
@@ -27,6 +27,9 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ) += abort-ev5tj.o | |||
27 | obj-$(CONFIG_CPU_ABRT_EV6) += abort-ev6.o | 27 | obj-$(CONFIG_CPU_ABRT_EV6) += abort-ev6.o |
28 | obj-$(CONFIG_CPU_ABRT_EV7) += abort-ev7.o | 28 | obj-$(CONFIG_CPU_ABRT_EV7) += abort-ev7.o |
29 | 29 | ||
30 | AFLAGS_abort-ev6.o :=-Wa,-march=armv6k | ||
31 | AFLAGS_abort-ev7.o :=-Wa,-march=armv7-a | ||
32 | |||
30 | obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o | 33 | obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o |
31 | obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o | 34 | obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o |
32 | obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o | 35 | obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o |
@@ -39,6 +42,9 @@ obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o | |||
39 | obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o | 42 | obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o |
40 | obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o | 43 | obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o |
41 | 44 | ||
45 | AFLAGS_cache-v6.o :=-Wa,-march=armv6 | ||
46 | AFLAGS_cache-v7.o :=-Wa,-march=armv7-a | ||
47 | |||
42 | obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o | 48 | obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o |
43 | obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o | 49 | obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o |
44 | obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o | 50 | obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o |
@@ -58,6 +64,9 @@ obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o | |||
58 | obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o | 64 | obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o |
59 | obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o | 65 | obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o |
60 | 66 | ||
67 | AFLAGS_tlb-v6.o :=-Wa,-march=armv6 | ||
68 | AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a | ||
69 | |||
61 | obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o | 70 | obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o |
62 | obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o | 71 | obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o |
63 | obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o | 72 | obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o |
@@ -84,6 +93,9 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o | |||
84 | obj-$(CONFIG_CPU_V6) += proc-v6.o | 93 | obj-$(CONFIG_CPU_V6) += proc-v6.o |
85 | obj-$(CONFIG_CPU_V7) += proc-v7.o | 94 | obj-$(CONFIG_CPU_V7) += proc-v7.o |
86 | 95 | ||
96 | AFLAGS_proc-v6.o :=-Wa,-march=armv6 | ||
97 | AFLAGS_proc-v7.o :=-Wa,-march=armv7-a | ||
98 | |||
87 | obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o | 99 | obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o |
88 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | 100 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o |
89 | obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o | 101 | obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o |
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index b270d6228fe2..62820eda84d9 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c | |||
@@ -11,6 +11,7 @@ | |||
11 | * it under the terms of the GNU General Public License version 2 as | 11 | * it under the terms of the GNU General Public License version 2 as |
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | #include <linux/moduleparam.h> | ||
14 | #include <linux/compiler.h> | 15 | #include <linux/compiler.h> |
15 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
16 | #include <linux/errno.h> | 17 | #include <linux/errno.h> |
@@ -77,6 +78,8 @@ static unsigned long ai_dword; | |||
77 | static unsigned long ai_multi; | 78 | static unsigned long ai_multi; |
78 | static int ai_usermode; | 79 | static int ai_usermode; |
79 | 80 | ||
81 | core_param(alignment, ai_usermode, int, 0600); | ||
82 | |||
80 | #define UM_WARN (1 << 0) | 83 | #define UM_WARN (1 << 0) |
81 | #define UM_FIXUP (1 << 1) | 84 | #define UM_FIXUP (1 << 1) |
82 | #define UM_SIGNAL (1 << 2) | 85 | #define UM_SIGNAL (1 << 2) |
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 5d180cb0bd94..c3154928bccd 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c | |||
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void) | |||
221 | if (!cpu_is_xsc3() || !xsc3_l2_present()) | 221 | if (!cpu_is_xsc3() || !xsc3_l2_present()) |
222 | return 0; | 222 | return 0; |
223 | 223 | ||
224 | if (!(get_cr() & CR_L2)) { | 224 | if (get_cr() & CR_L2) { |
225 | pr_info("XScale3 L2 cache enabled.\n"); | 225 | pr_info("XScale3 L2 cache enabled.\n"); |
226 | adjust_cr(CR_L2, CR_L2); | ||
227 | xsc3_l2_inv_all(); | 226 | xsc3_l2_inv_all(); |
228 | } | ||
229 | 227 | ||
230 | outer_cache.inv_range = xsc3_l2_inv_range; | 228 | outer_cache.inv_range = xsc3_l2_inv_range; |
231 | outer_cache.clean_range = xsc3_l2_clean_range; | 229 | outer_cache.clean_range = xsc3_l2_clean_range; |
232 | outer_cache.flush_range = xsc3_l2_flush_range; | 230 | outer_cache.flush_range = xsc3_l2_flush_range; |
231 | } | ||
233 | 232 | ||
234 | return 0; | 233 | return 0; |
235 | } | 234 | } |
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 52c40d155672..a04ffbbbe253 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
@@ -616,7 +616,7 @@ void __init mem_init(void) | |||
616 | "%dK data, %dK init, %luK highmem)\n", | 616 | "%dK data, %dK init, %luK highmem)\n", |
617 | nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10, | 617 | nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10, |
618 | datasize >> 10, initsize >> 10, | 618 | datasize >> 10, initsize >> 10, |
619 | (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); | 619 | totalhigh_pages << (PAGE_SHIFT-10)); |
620 | 620 | ||
621 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { | 621 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { |
622 | extern int sysctl_overcommit_memory; | 622 | extern int sysctl_overcommit_memory; |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 1708da82da96..761ffede6a23 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
@@ -1067,4 +1067,6 @@ void setup_mm_for_reboot(char mode) | |||
1067 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); | 1067 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); |
1068 | flush_pmd_entry(pmd); | 1068 | flush_pmd_entry(pmd); |
1069 | } | 1069 | } |
1070 | |||
1071 | local_flush_tlb_all(); | ||
1070 | } | 1072 | } |
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 3f9cd3d8f6d5..795dc615f43b 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S | |||
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area) | |||
41 | ENTRY(cpu_arm7_data_abort) | 41 | ENTRY(cpu_arm7_data_abort) |
42 | mrc p15, 0, r1, c5, c0, 0 @ get FSR | 42 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
43 | mrc p15, 0, r0, c6, c0, 0 @ get FAR | 43 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
44 | ldr r8, [r0] @ read arm instruction | 44 | ldr r8, [r2] @ read arm instruction |
45 | tst r8, #1 << 20 @ L = 0 -> write? | 45 | tst r8, #1 << 20 @ L = 0 -> write? |
46 | orreq r1, r1, #1 << 11 @ yes. | 46 | orreq r1, r1, #1 << 11 @ yes. |
47 | and r7, r8, #15 << 24 | 47 | and r7, r8, #15 << 24 |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 395cc90c6613..7a5337ed7d68 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin) | |||
59 | * to what would be the reset vector. | 59 | * to what would be the reset vector. |
60 | * | 60 | * |
61 | * - loc - location to jump to for soft reset | 61 | * - loc - location to jump to for soft reset |
62 | * | ||
63 | * It is assumed that: | ||
64 | */ | 62 | */ |
65 | .align 5 | 63 | .align 5 |
66 | ENTRY(cpu_v6_reset) | 64 | ENTRY(cpu_v6_reset) |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3a285218fd15..7aaf88a3b7aa 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -45,7 +45,14 @@ ENTRY(cpu_v7_proc_init) | |||
45 | ENDPROC(cpu_v7_proc_init) | 45 | ENDPROC(cpu_v7_proc_init) |
46 | 46 | ||
47 | ENTRY(cpu_v7_proc_fin) | 47 | ENTRY(cpu_v7_proc_fin) |
48 | mov pc, lr | 48 | stmfd sp!, {lr} |
49 | cpsid if @ disable interrupts | ||
50 | bl v7_flush_kern_cache_all | ||
51 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | ||
52 | bic r0, r0, #0x1000 @ ...i............ | ||
53 | bic r0, r0, #0x0006 @ .............ca. | ||
54 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | ||
55 | ldmfd sp!, {pc} | ||
49 | ENDPROC(cpu_v7_proc_fin) | 56 | ENDPROC(cpu_v7_proc_fin) |
50 | 57 | ||
51 | /* | 58 | /* |
@@ -56,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin) | |||
56 | * to what would be the reset vector. | 63 | * to what would be the reset vector. |
57 | * | 64 | * |
58 | * - loc - location to jump to for soft reset | 65 | * - loc - location to jump to for soft reset |
59 | * | ||
60 | * It is assumed that: | ||
61 | */ | 66 | */ |
62 | .align 5 | 67 | .align 5 |
63 | ENTRY(cpu_v7_reset) | 68 | ENTRY(cpu_v7_reset) |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 96456f548798..8e4f6dca8997 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -407,6 +407,13 @@ __xsc3_setup: | |||
407 | 407 | ||
408 | adr r5, xsc3_crval | 408 | adr r5, xsc3_crval |
409 | ldmia r5, {r5, r6} | 409 | ldmia r5, {r5, r6} |
410 | |||
411 | #ifdef CONFIG_CACHE_XSC3L2 | ||
412 | mrc p15, 1, r0, c0, c0, 1 @ get L2 present information | ||
413 | ands r0, r0, #0xf8 | ||
414 | orrne r6, r6, #(1 << 26) @ enable L2 if present | ||
415 | #endif | ||
416 | |||
410 | mrc p15, 0, r0, c1, c0, 0 @ get control register | 417 | mrc p15, 0, r0, c1, c0, 0 @ get control register |
411 | bic r0, r0, r5 @ ..V. ..R. .... ..A. | 418 | bic r0, r0, r5 @ ..V. ..R. .... ..A. |
412 | orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) | 419 | orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) |
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index a26a605b73bd..0cb1848bd876 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S | |||
@@ -40,7 +40,6 @@ ENTRY(v7wbi_flush_user_tlb_range) | |||
40 | asid r3, r3 @ mask ASID | 40 | asid r3, r3 @ mask ASID |
41 | orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA | 41 | orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA |
42 | mov r1, r1, lsl #PAGE_SHIFT | 42 | mov r1, r1, lsl #PAGE_SHIFT |
43 | vma_vm_flags r2, r2 @ get vma->vm_flags | ||
44 | 1: | 43 | 1: |
45 | #ifdef CONFIG_SMP | 44 | #ifdef CONFIG_SMP |
46 | mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) | 45 | mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) |