diff options
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 65 |
1 files changed, 59 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 14075979bcba..42af97664c9d 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -181,6 +181,17 @@ ENTRY(cpu_xscale_do_idle) | |||
181 | /* ================================= CACHE ================================ */ | 181 | /* ================================= CACHE ================================ */ |
182 | 182 | ||
183 | /* | 183 | /* |
184 | * flush_icache_all() | ||
185 | * | ||
186 | * Unconditionally clean and invalidate the entire icache. | ||
187 | */ | ||
188 | ENTRY(xscale_flush_icache_all) | ||
189 | mov r0, #0 | ||
190 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
191 | mov pc, lr | ||
192 | ENDPROC(xscale_flush_icache_all) | ||
193 | |||
194 | /* | ||
184 | * flush_user_cache_all() | 195 | * flush_user_cache_all() |
185 | * | 196 | * |
186 | * Invalidate all cache entries in a particular address | 197 | * Invalidate all cache entries in a particular address |
@@ -384,7 +395,7 @@ ENTRY(xscale_dma_a0_map_area) | |||
384 | teq r2, #DMA_TO_DEVICE | 395 | teq r2, #DMA_TO_DEVICE |
385 | beq xscale_dma_clean_range | 396 | beq xscale_dma_clean_range |
386 | b xscale_dma_flush_range | 397 | b xscale_dma_flush_range |
387 | ENDPROC(xscsale_dma_a0_map_area) | 398 | ENDPROC(xscale_dma_a0_map_area) |
388 | 399 | ||
389 | /* | 400 | /* |
390 | * dma_unmap_area(start, size, dir) | 401 | * dma_unmap_area(start, size, dir) |
@@ -397,6 +408,7 @@ ENTRY(xscale_dma_unmap_area) | |||
397 | ENDPROC(xscale_dma_unmap_area) | 408 | ENDPROC(xscale_dma_unmap_area) |
398 | 409 | ||
399 | ENTRY(xscale_cache_fns) | 410 | ENTRY(xscale_cache_fns) |
411 | .long xscale_flush_icache_all | ||
400 | .long xscale_flush_kern_cache_all | 412 | .long xscale_flush_kern_cache_all |
401 | .long xscale_flush_user_cache_all | 413 | .long xscale_flush_user_cache_all |
402 | .long xscale_flush_user_cache_range | 414 | .long xscale_flush_user_cache_range |
@@ -488,8 +500,8 @@ ENTRY(cpu_xscale_set_pte_ext) | |||
488 | @ | 500 | @ |
489 | @ Erratum 40: must set memory to write-through for user read-only pages | 501 | @ Erratum 40: must set memory to write-through for user read-only pages |
490 | @ | 502 | @ |
491 | and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2) | 503 | and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) |
492 | teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | 504 | teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY |
493 | 505 | ||
494 | moveq r1, #L_PTE_MT_WRITETHROUGH | 506 | moveq r1, #L_PTE_MT_WRITETHROUGH |
495 | and r1, r1, #L_PTE_MT_MASK | 507 | and r1, r1, #L_PTE_MT_MASK |
@@ -501,12 +513,50 @@ ENTRY(cpu_xscale_set_pte_ext) | |||
501 | xscale_set_pte_ext_epilogue | 513 | xscale_set_pte_ext_epilogue |
502 | mov pc, lr | 514 | mov pc, lr |
503 | 515 | ||
504 | |||
505 | .ltorg | 516 | .ltorg |
506 | |||
507 | .align | 517 | .align |
508 | 518 | ||
509 | __INIT | 519 | .globl cpu_xscale_suspend_size |
520 | .equ cpu_xscale_suspend_size, 4 * 7 | ||
521 | #ifdef CONFIG_PM_SLEEP | ||
522 | ENTRY(cpu_xscale_do_suspend) | ||
523 | stmfd sp!, {r4 - r10, lr} | ||
524 | mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode | ||
525 | mrc p15, 0, r5, c15, c1, 0 @ CP access reg | ||
526 | mrc p15, 0, r6, c13, c0, 0 @ PID | ||
527 | mrc p15, 0, r7, c3, c0, 0 @ domain ID | ||
528 | mrc p15, 0, r8, c2, c0, 0 @ translation table base addr | ||
529 | mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg | ||
530 | mrc p15, 0, r10, c1, c0, 0 @ control reg | ||
531 | bic r4, r4, #2 @ clear frequency change bit | ||
532 | stmia r0, {r4 - r10} @ store cp regs | ||
533 | ldmfd sp!, {r4 - r10, pc} | ||
534 | ENDPROC(cpu_xscale_do_suspend) | ||
535 | |||
536 | ENTRY(cpu_xscale_do_resume) | ||
537 | ldmia r0, {r4 - r10} @ load cp regs | ||
538 | mov ip, #0 | ||
539 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
540 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB | ||
541 | mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. | ||
542 | mcr p15, 0, r5, c15, c1, 0 @ CP access reg | ||
543 | mcr p15, 0, r6, c13, c0, 0 @ PID | ||
544 | mcr p15, 0, r7, c3, c0, 0 @ domain ID | ||
545 | mcr p15, 0, r8, c2, c0, 0 @ translation table base addr | ||
546 | mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg | ||
547 | mov r0, r10 @ control register | ||
548 | mov r2, r8, lsr #14 @ get TTB0 base | ||
549 | mov r2, r2, lsl #14 | ||
550 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | ||
551 | PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE | ||
552 | b cpu_resume_mmu | ||
553 | ENDPROC(cpu_xscale_do_resume) | ||
554 | #else | ||
555 | #define cpu_xscale_do_suspend 0 | ||
556 | #define cpu_xscale_do_resume 0 | ||
557 | #endif | ||
558 | |||
559 | __CPUINIT | ||
510 | 560 | ||
511 | .type __xscale_setup, #function | 561 | .type __xscale_setup, #function |
512 | __xscale_setup: | 562 | __xscale_setup: |
@@ -553,6 +603,9 @@ ENTRY(xscale_processor_functions) | |||
553 | .word cpu_xscale_dcache_clean_area | 603 | .word cpu_xscale_dcache_clean_area |
554 | .word cpu_xscale_switch_mm | 604 | .word cpu_xscale_switch_mm |
555 | .word cpu_xscale_set_pte_ext | 605 | .word cpu_xscale_set_pte_ext |
606 | .word cpu_xscale_suspend_size | ||
607 | .word cpu_xscale_do_suspend | ||
608 | .word cpu_xscale_do_resume | ||
556 | .size xscale_processor_functions, . - xscale_processor_functions | 609 | .size xscale_processor_functions, . - xscale_processor_functions |
557 | 610 | ||
558 | .section ".rodata" | 611 | .section ".rodata" |