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-rw-r--r--arch/arm/mm/proc-xsc3.S32
1 files changed, 28 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8e4f6dca8997..e5797f1c1db7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
257 * - start - virtual start address 257 * - start - virtual start address
258 * - end - virtual end address 258 * - end - virtual end address
259 */ 259 */
260ENTRY(xsc3_dma_inv_range) 260xsc3_dma_inv_range:
261 tst r0, #CACHELINESIZE - 1 261 tst r0, #CACHELINESIZE - 1
262 bic r0, r0, #CACHELINESIZE - 1 262 bic r0, r0, #CACHELINESIZE - 1
263 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line 263 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range)
278 * - start - virtual start address 278 * - start - virtual start address
279 * - end - virtual end address 279 * - end - virtual end address
280 */ 280 */
281ENTRY(xsc3_dma_clean_range) 281xsc3_dma_clean_range:
282 bic r0, r0, #CACHELINESIZE - 1 282 bic r0, r0, #CACHELINESIZE - 1
2831: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 2831: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
284 add r0, r0, #CACHELINESIZE 284 add r0, r0, #CACHELINESIZE
@@ -304,6 +304,30 @@ ENTRY(xsc3_dma_flush_range)
304 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 304 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
305 mov pc, lr 305 mov pc, lr
306 306
307/*
308 * dma_map_area(start, size, dir)
309 * - start - kernel virtual start address
310 * - size - size of region
311 * - dir - DMA direction
312 */
313ENTRY(xsc3_dma_map_area)
314 add r1, r1, r0
315 cmp r2, #DMA_TO_DEVICE
316 beq xsc3_dma_clean_range
317 bcs xsc3_dma_inv_range
318 b xsc3_dma_flush_range
319ENDPROC(xsc3_dma_map_area)
320
321/*
322 * dma_unmap_area(start, size, dir)
323 * - start - kernel virtual start address
324 * - size - size of region
325 * - dir - DMA direction
326 */
327ENTRY(xsc3_dma_unmap_area)
328 mov pc, lr
329ENDPROC(xsc3_dma_unmap_area)
330
307ENTRY(xsc3_cache_fns) 331ENTRY(xsc3_cache_fns)
308 .long xsc3_flush_kern_cache_all 332 .long xsc3_flush_kern_cache_all
309 .long xsc3_flush_user_cache_all 333 .long xsc3_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(xsc3_cache_fns)
311 .long xsc3_coherent_kern_range 335 .long xsc3_coherent_kern_range
312 .long xsc3_coherent_user_range 336 .long xsc3_coherent_user_range
313 .long xsc3_flush_kern_dcache_area 337 .long xsc3_flush_kern_dcache_area
314 .long xsc3_dma_inv_range 338 .long xsc3_dma_map_area
315 .long xsc3_dma_clean_range 339 .long xsc3_dma_unmap_area
316 .long xsc3_dma_flush_range 340 .long xsc3_dma_flush_range
317 341
318ENTRY(cpu_xsc3_dcache_clean_area) 342ENTRY(cpu_xsc3_dcache_clean_area)