1 files changed, 54 insertions, 11 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c73a7301ff7..7ef3ad05df39 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -98,9 +98,11 @@ ENTRY(cpu_v7_do_suspend)
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         stmia   r0!, {r4 - r5}
+#ifdef CONFIG_MMU
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
+#endif
         mrc     p15, 0, r8, c1, c0, 0   @ Control register
         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
@@ -110,13 +112,14 @@ ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
         mov     ip, #0
-        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
         ldmia   r0!, {r4 - r5}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         ldmia   r0, {r6 - r11}
+#ifdef CONFIG_MMU
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 #ifndef CONFIG_ARM_LPAE
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +128,15 @@ ENTRY(cpu_v7_do_resume)
         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
-        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r9                  @ Is it already set?
-        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
-        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
+#endif  /* CONFIG_MMU */
+        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         isb
         dsb
         mov     r0, r8                  @ control register
@@ -140,6 +144,29 @@ ENTRY(cpu_v7_do_resume)
 ENDPROC(cpu_v7_do_resume)
 #endif
 
+#ifdef CONFIG_CPU_PJ4B
+        globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
+        globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
+        globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
+        globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
+        globl_equ       cpu_pj4b_reset,         cpu_v7_reset
+#ifdef CONFIG_PJ4B_ERRATA_4742
+ENTRY(cpu_pj4b_do_idle)
+        dsb                                     @ WFI may enter a low-power mode
+        wfi
+        dsb                                     @barrier
+        mov     pc, lr
+ENDPROC(cpu_pj4b_do_idle)
+#else
+        globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
+#endif
+        globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
+        globl_equ       cpu_pj4b_do_suspend,    cpu_v7_do_suspend
+        globl_equ       cpu_pj4b_do_resume,     cpu_v7_do_resume
+        globl_equ       cpu_pj4b_suspend_size,  cpu_v7_suspend_size
+
+#endif
+
         __CPUINIT
 
 /*
@@ -155,7 +182,8 @@ ENDPROC(cpu_v7_do_resume)
  */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
-        mov     r10, #(1 << 0)                  @ TLB ops broadcasting
+__v7_cr7mp_setup:
+        mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
         b       1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
@@ -350,6 +378,9 @@ __v7_setup_stack:
 
         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+#ifdef CONFIG_CPU_PJ4B
+        define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+#endif
 
         .section ".rodata"
 
@@ -362,7 +393,7 @@ __v7_setup_stack:
         /*
          * Standard v7 proc info content
          */
-.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -375,7 +406,7 @@ __v7_setup_stack:
         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
         .long   cpu_v7_name
-        .long   v7_processor_functions
+        .long   \proc_fns
         .long   v7wbi_tlb_fns
         .long   v6_user_fns
         .long   v7_cache_fns
@@ -407,12 +438,24 @@ __v7_ca9mp_proc_info:
         /*
          * Marvell PJ4B processor.
          */
+#ifdef CONFIG_CPU_PJ4B
         .type   __v7_pj4b_proc_info, #object
 __v7_pj4b_proc_info:
-        .long   0x562f5840
-        .long   0xfffffff0
-        __v7_proc __v7_pj4b_setup
+        .long   0x560f5800
+        .long   0xff0fff00
+        __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
+#endif
+
+        /*
+         * ARM Ltd. Cortex R7 processor.
+         */
+        .type   __v7_cr7mp_proc_info, #object
+__v7_cr7mp_proc_info:
+        .long   0x410fc170
+        .long   0xff0ffff0
+        __v7_proc __v7_cr7mp_setup
+        .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 
         /*
          * ARM Ltd. Cortex A7 processor.