1 files changed, 10 insertions, 16 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7e9b5bf910c1..0404ccbb8aa3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
  *      on.  Return in r0 the new CP15 C1 control register setting.
  *
- *      We automatically detect if we have a Harvard cache, and use the
- *      Harvard cache control instructions insead of the unified cache
- *      control instructions.
- *
  *      This should be able to cover all ARMv7 cores.
  *
  *      It is assumed that:
@@ -251,9 +247,7 @@ __v7_setup:
 #endif
 
 3:      mov     r10, #0
-#ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-#endif
         dsb
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
@@ -330,16 +324,6 @@ __v7_ca5mp_proc_info:
         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 
         /*
-         * ARM Ltd. Cortex A7 processor.
-         */
-        .type   __v7_ca7mp_proc_info, #object
-__v7_ca7mp_proc_info:
-        .long   0x410fc070
-        .long   0xff0ffff0
-        __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
-        .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
-
-        /*
          * ARM Ltd. Cortex A9 processor.
          */
         .type   __v7_ca9mp_proc_info, #object
@@ -351,6 +335,16 @@ __v7_ca9mp_proc_info:
 #endif  /* CONFIG_ARM_LPAE */
 
         /*
+         * ARM Ltd. Cortex A7 processor.
+         */
+        .type   __v7_ca7mp_proc_info, #object
+__v7_ca7mp_proc_info:
+        .long   0x410fc070
+        .long   0xff0ffff0
+        __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+        .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
+
+        /*
          * ARM Ltd. Cortex A15 processor.
          */
         .type   __v7_ca15mp_proc_info, #object