1 files changed, 12 insertions, 17 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a67e26f3dce2..34e424041927 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -12,7 +12,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
@@ -105,26 +105,19 @@ ENDPROC(cpu_v7_switch_mm)
  *                (hardware version is stored at -1024 bytes)
  *      - pte   - PTE value to store
  *      - ext   - value for extended PTE bits
- *
- *      Permissions:
- *        YUWD  APX AP1 AP0     SVC     User
- *        0xxx   0   0   0      no acc  no acc
- *        100x   1   0   1      r/o     no acc
- *        10x0   1   0   1      r/o     no acc
- *        1011   0   0   1      r/w     no acc
- *        110x   0   1   0      r/w     r/o
- *        11x0   0   1   0      r/w     r/o
- *        1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
         str     r1, [r0], #-2048                @ linux version
 
         bic     r3, r1, #0x000003f0
-        bic     r3, r3, #0x00000003
+        bic     r3, r3, #PTE_TYPE_MASK
         orr     r3, r3, r2
         orr     r3, r3, #PTE_EXT_AP0 | 2
 
+        tst     r2, #1 << 4
+        orrne   r3, r3, #PTE_EXT_TEX(1)
+
         tst     r1, #L_PTE_WRITE
         tstne   r1, #L_PTE_DIRTY
         orreq   r3, r3, #PTE_EXT_APX
@@ -134,13 +127,11 @@ ENTRY(cpu_v7_set_pte_ext)
         tstne   r3, #PTE_EXT_APX
         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 
-        tst     r1, #L_PTE_YOUNG
-        biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
         tst     r1, #L_PTE_EXEC
         orreq   r3, r3, #PTE_EXT_XN
 
-        tst     r1, #L_PTE_PRESENT
+        tst     r1, #L_PTE_YOUNG
+        tstne   r1, #L_PTE_PRESENT
         moveq   r3, #0
 
         str     r3, [r0]
@@ -189,6 +180,10 @@ __v7_setup:
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
+        ldr     r5, =0x40e040e0
+        ldr     r6, =0xff0aa1a8
+        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
+        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
         adr     r5, v7_crval
         ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
@@ -205,7 +200,7 @@ ENDPROC(__v7_setup)
          */
         .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
+        crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
 
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers