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-rw-r--r--arch/arm/mm/proc-v7.S25
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 07b0269dafa7..e0acc5ae6f6f 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
77 * - we are not using split page tables 77 * - we are not using split page tables
78 */ 78 */
79ENTRY(cpu_v7_switch_mm) 79ENTRY(cpu_v7_switch_mm)
80#ifdef CONFIG_MMU
80 mov r2, #0 81 mov r2, #0
81 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 82 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
82 orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 83 orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
@@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
86 isb 87 isb
87 mcr p15, 0, r1, c13, c0, 1 @ set context ID 88 mcr p15, 0, r1, c13, c0, 1 @ set context ID
88 isb 89 isb
90#endif
89 mov pc, lr 91 mov pc, lr
90 92
91/* 93/*
@@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm)
109 * 1111 0 1 1 r/w r/w 111 * 1111 0 1 1 r/w r/w
110 */ 112 */
111ENTRY(cpu_v7_set_pte_ext) 113ENTRY(cpu_v7_set_pte_ext)
114#ifdef CONFIG_MMU
112 str r1, [r0], #-2048 @ linux version 115 str r1, [r0], #-2048 @ linux version
113 116
114 bic r3, r1, #0x000003f0 117 bic r3, r1, #0x000003f0
@@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext)
136 139
137 str r3, [r0] 140 str r3, [r0]
138 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 141 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
142#endif
139 mov pc, lr 143 mov pc, lr
140 144
141cpu_v7_name: 145cpu_v7_name:
@@ -169,6 +173,7 @@ __v7_setup:
169 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 173 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
170#endif 174#endif
171 dsb 175 dsb
176#ifdef CONFIG_MMU
172 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 177 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
173 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 178 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
174 orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 179 orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
@@ -176,11 +181,12 @@ __v7_setup:
176 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 181 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
177 mov r10, #0x1f @ domains 0, 1 = manager 182 mov r10, #0x1f @ domains 0, 1 = manager
178 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 183 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
179 mrc p15, 0, r0, c1, c0, 0 @ read control register 184#endif
180 ldr r10, cr1_clear @ get mask for bits to clear 185 adr r5, v7_crval
181 bic r0, r0, r10 @ clear bits them 186 ldmia r5, {r5, r6}
182 ldr r10, cr1_set @ get mask for bits to set 187 mrc p15, 0, r0, c1, c0, 0 @ read control register
183 orr r0, r0, r10 @ set them 188 bic r0, r0, r5 @ clear bits them
189 orr r0, r0, r6 @ set them
184 mov pc, lr @ return to head.S:__ret 190 mov pc, lr @ return to head.S:__ret
185 191
186 /* 192 /*
@@ -189,12 +195,9 @@ __v7_setup:
189 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 195 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
190 * 0 110 0011 1.00 .111 1101 < we want 196 * 0 110 0011 1.00 .111 1101 < we want
191 */ 197 */
192 .type cr1_clear, #object 198 .type v7_crval, #object
193 .type cr1_set, #object 199v7_crval:
194cr1_clear: 200 crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
195 .word 0x0120c302
196cr1_set:
197 .word 0x00c0387d
198 201
199__v7_setup_stack: 202__v7_setup_stack:
200 .space 4 * 11 @ 11 registers 203 .space 4 * 11 @ 11 registers