diff options
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 718f4782ee8b..07b0269dafa7 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -176,16 +176,6 @@ __v7_setup: | |||
| 176 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 176 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
| 177 | mov r10, #0x1f @ domains 0, 1 = manager | 177 | mov r10, #0x1f @ domains 0, 1 = manager |
| 178 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | 178 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register |
| 179 | #ifndef CONFIG_CPU_L2CACHE_DISABLE | ||
| 180 | @ L2 cache configuration in the L2 aux control register | ||
| 181 | mrc p15, 1, r10, c9, c0, 2 | ||
| 182 | bic r10, r10, #(1 << 16) @ L2 outer cache | ||
| 183 | mcr p15, 1, r10, c9, c0, 2 | ||
| 184 | @ L2 cache is enabled in the aux control register | ||
| 185 | mrc p15, 0, r10, c1, c0, 1 | ||
| 186 | orr r10, r10, #2 | ||
| 187 | mcr p15, 0, r10, c1, c0, 1 | ||
| 188 | #endif | ||
| 189 | mrc p15, 0, r0, c1, c0, 0 @ read control register | 179 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
| 190 | ldr r10, cr1_clear @ get mask for bits to clear | 180 | ldr r10, cr1_clear @ get mask for bits to clear |
| 191 | bic r0, r0, r10 @ clear bits them | 181 | bic r0, r0, r10 @ clear bits them |