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-rw-r--r--arch/arm/mm/proc-v7.S47
1 files changed, 32 insertions, 15 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 197f21bed5e9..53cbe2225153 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32 32
33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS PMD_SECT_WB 35#define PMD_FLAGS_UP PMD_SECT_WB
37#else 36
38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41#endif
42 40
43ENTRY(cpu_v7_proc_init) 41ENTRY(cpu_v7_proc_init)
44 mov pc, lr 42 mov pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
105#ifdef CONFIG_MMU 103#ifdef CONFIG_MMU
106 mov r2, #0 104 mov r2, #0
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 orr r0, r0, #TTB_FLAGS 106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
109#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
110 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111#endif 110#endif
@@ -169,7 +168,7 @@ cpu_v7_name:
169 .ascii "ARMv7 Processor" 168 .ascii "ARMv7 Processor"
170 .align 169 .align
171 170
172 __INIT 171 __CPUINIT
173 172
174/* 173/*
175 * __v7_setup 174 * __v7_setup
@@ -188,7 +187,8 @@ cpu_v7_name:
188 */ 187 */
189__v7_ca9mp_setup: 188__v7_ca9mp_setup:
190#ifdef CONFIG_SMP 189#ifdef CONFIG_SMP
191 mrc p15, 0, r0, c1, c0, 1 190 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
191 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
@@ -270,7 +270,8 @@ __v7_setup:
270#ifdef CONFIG_MMU 270#ifdef CONFIG_MMU
271 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 271 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
272 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 272 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
273 orr r4, r4, #TTB_FLAGS 273 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
274 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
274 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 275 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
275 mov r10, #0x1f @ domains 0, 1 = manager 276 mov r10, #0x1f @ domains 0, 1 = manager
276 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 277 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
@@ -332,6 +333,8 @@ v7_crval:
332__v7_setup_stack: 333__v7_setup_stack:
333 .space 4 * 11 @ 11 registers 334 .space 4 * 11 @ 11 registers
334 335
336 __INITDATA
337
335 .type v7_processor_functions, #object 338 .type v7_processor_functions, #object
336ENTRY(v7_processor_functions) 339ENTRY(v7_processor_functions)
337 .word v7_early_abort 340 .word v7_early_abort
@@ -345,6 +348,8 @@ ENTRY(v7_processor_functions)
345 .word cpu_v7_set_pte_ext 348 .word cpu_v7_set_pte_ext
346 .size v7_processor_functions, . - v7_processor_functions 349 .size v7_processor_functions, . - v7_processor_functions
347 350
351 .section ".rodata"
352
348 .type cpu_arch_name, #object 353 .type cpu_arch_name, #object
349cpu_arch_name: 354cpu_arch_name:
350 .asciz "armv7" 355 .asciz "armv7"
@@ -362,10 +367,16 @@ cpu_elf_name:
362__v7_ca9mp_proc_info: 367__v7_ca9mp_proc_info:
363 .long 0x410fc090 @ Required ID value 368 .long 0x410fc090 @ Required ID value
364 .long 0xff0ffff0 @ Mask for ID 369 .long 0xff0ffff0 @ Mask for ID
365 .long PMD_TYPE_SECT | \ 370 ALT_SMP(.long \
371 PMD_TYPE_SECT | \
366 PMD_SECT_AP_WRITE | \ 372 PMD_SECT_AP_WRITE | \
367 PMD_SECT_AP_READ | \ 373 PMD_SECT_AP_READ | \
368 PMD_FLAGS 374 PMD_FLAGS_SMP)
375 ALT_UP(.long \
376 PMD_TYPE_SECT | \
377 PMD_SECT_AP_WRITE | \
378 PMD_SECT_AP_READ | \
379 PMD_FLAGS_UP)
369 .long PMD_TYPE_SECT | \ 380 .long PMD_TYPE_SECT | \
370 PMD_SECT_XN | \ 381 PMD_SECT_XN | \
371 PMD_SECT_AP_WRITE | \ 382 PMD_SECT_AP_WRITE | \
@@ -388,10 +399,16 @@ __v7_ca9mp_proc_info:
388__v7_proc_info: 399__v7_proc_info:
389 .long 0x000f0000 @ Required ID value 400 .long 0x000f0000 @ Required ID value
390 .long 0x000f0000 @ Mask for ID 401 .long 0x000f0000 @ Mask for ID
391 .long PMD_TYPE_SECT | \ 402 ALT_SMP(.long \
403 PMD_TYPE_SECT | \
404 PMD_SECT_AP_WRITE | \
405 PMD_SECT_AP_READ | \
406 PMD_FLAGS_SMP)
407 ALT_UP(.long \
408 PMD_TYPE_SECT | \
392 PMD_SECT_AP_WRITE | \ 409 PMD_SECT_AP_WRITE | \
393 PMD_SECT_AP_READ | \ 410 PMD_SECT_AP_READ | \
394 PMD_FLAGS 411 PMD_FLAGS_UP)
395 .long PMD_TYPE_SECT | \ 412 .long PMD_TYPE_SECT | \
396 PMD_SECT_XN | \ 413 PMD_SECT_XN | \
397 PMD_SECT_AP_WRITE | \ 414 PMD_SECT_AP_WRITE | \