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-rw-r--r--arch/arm/mm/proc-v7.S4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 350f6a74992b..3a3c015f8d5c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,6 +169,7 @@ __v7_ca15mp_setup:
169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits 169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
170 mcreq p15, 0, r0, c1, c0, 1 170 mcreq p15, 0, r0, c1, c0, 1
171#endif 171#endif
172 b __v7_setup
172 173
173__v7_pj4b_setup: 174__v7_pj4b_setup:
174#ifdef CONFIG_CPU_PJ4B 175#ifdef CONFIG_CPU_PJ4B
@@ -245,7 +246,8 @@ __v7_setup:
245 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 246 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
246 teq r0, r10 247 teq r0, r10
247 bne 2f 248 bne 2f
248#ifdef CONFIG_ARM_ERRATA_430973 249#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
250
249 teq r5, #0x00100000 @ only present in r1p* 251 teq r5, #0x00100000 @ only present in r1p*
250 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 252 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
251 orreq r10, r10, #(1 << 6) @ set IBE to 1 253 orreq r10, r10, #(1 << 6) @ set IBE to 1