1 files changed, 7 insertions, 2 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 9b9ff5d949fd..7401f4d7e676 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -148,8 +148,11 @@ ENTRY(cpu_v7_set_pte_ext)
 
         tst     r1, #L_PTE_USER
         orrne   r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+        @ allow kernel read/write access to read-only user pages
         tstne   r3, #PTE_EXT_APX
         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
         tst     r1, #L_PTE_EXEC
         orreq   r3, r3, #PTE_EXT_XN
@@ -273,8 +276,6 @@ __v7_setup:
         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
-        mov     r10, #0x1f                      @ domains 0, 1 = manager
-        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
         /*
          * Memory region attributes with SCTLR.TRE=1
          *
@@ -313,6 +314,10 @@ __v7_setup:
 #ifdef CONFIG_CPU_ENDIAN_BE8
         orr     r6, r6, #1 << 25                @ big-endian page tables
 #endif
+#ifdef CONFIG_SWP_EMULATE
+        orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
+        bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
+#endif
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them