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-rw-r--r--arch/arm/mm/proc-v6.S15
1 files changed, 1 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index eb42e5b94863..bf760ea2f789 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -17,10 +17,6 @@
17#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19 19
20#ifdef CONFIG_SMP
21#include <asm/hardware/arm_scu.h>
22#endif
23
24#include "proc-macros.S" 20#include "proc-macros.S"
25 21
26#define D_CACHE_LINE_SIZE 32 22#define D_CACHE_LINE_SIZE 32
@@ -187,20 +183,10 @@ cpu_v6_name:
187 */ 183 */
188__v6_setup: 184__v6_setup:
189#ifdef CONFIG_SMP 185#ifdef CONFIG_SMP
190 /* Set up the SCU on core 0 only */
191 mrc p15, 0, r0, c0, c0, 5 @ CPU core number
192 ands r0, r0, #15
193 ldreq r0, =SCU_BASE
194 ldreq r5, [r0, #SCU_CTRL]
195 orreq r5, r5, #1
196 streq r5, [r0, #SCU_CTRL]
197
198#ifndef CONFIG_CPU_DCACHE_DISABLE
199 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 186 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
200 orr r0, r0, #0x20 187 orr r0, r0, #0x20
201 mcr p15, 0, r0, c1, c0, 1 188 mcr p15, 0, r0, c1, c0, 1
202#endif 189#endif
203#endif
204 190
205 mov r0, #0 191 mov r0, #0
206 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 192 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
@@ -240,6 +226,7 @@ ENTRY(v6_processor_functions)
240 .word cpu_v6_dcache_clean_area 226 .word cpu_v6_dcache_clean_area
241 .word cpu_v6_switch_mm 227 .word cpu_v6_switch_mm
242 .word cpu_v6_set_pte_ext 228 .word cpu_v6_set_pte_ext
229 .word pabort_noifar
243 .size v6_processor_functions, . - v6_processor_functions 230 .size v6_processor_functions, . - v6_processor_functions
244 231
245 .type cpu_arch_name, #object 232 .type cpu_arch_name, #object