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-rw-r--r--arch/arm/mm/proc-v6.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 832b6bdc192c..7c99cb4c8e4f 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -124,7 +124,7 @@ ENTRY(cpu_v6_set_pte_ext)
124/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 124/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
125.globl cpu_v6_suspend_size 125.globl cpu_v6_suspend_size
126.equ cpu_v6_suspend_size, 4 * 8 126.equ cpu_v6_suspend_size, 4 * 8
127#ifdef CONFIG_PM 127#ifdef CONFIG_PM_SLEEP
128ENTRY(cpu_v6_do_suspend) 128ENTRY(cpu_v6_do_suspend)
129 stmfd sp!, {r4 - r11, lr} 129 stmfd sp!, {r4 - r11, lr}
130 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 130 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
@@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend)
132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
135 mrc p15, 0, r9, c1, c0, 1 @ auxillary control register 135 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control 136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
137 mrc p15, 0, r11, c1, c0, 0 @ control register 137 mrc p15, 0, r11, c1, c0, 0 @ control register
138 stmia r0, {r4 - r11} 138 stmia r0, {r4 - r11}
@@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume)
151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
154 mcr p15, 0, r9, c1, c0, 1 @ auxillary control register 154 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control 155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
157 mcr p15, 0, ip, c7, c5, 4 @ ISB 157 mcr p15, 0, ip, c7, c5, 4 @ ISB