diff options
Diffstat (limited to 'arch/arm/mm/proc-sa1100.S')
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 37 |
1 files changed, 5 insertions, 32 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 41f21f2dd8ff..777ad99c1439 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
@@ -30,30 +30,6 @@ | |||
30 | * the cache line size of the I and D cache | 30 | * the cache line size of the I and D cache |
31 | */ | 31 | */ |
32 | #define DCACHELINESIZE 32 | 32 | #define DCACHELINESIZE 32 |
33 | #define FLUSH_OFFSET 32768 | ||
34 | |||
35 | .macro flush_1100_dcache rd, ra, re | ||
36 | ldr \rd, =flush_base | ||
37 | ldr \ra, [\rd] | ||
38 | eor \ra, \ra, #FLUSH_OFFSET | ||
39 | str \ra, [\rd] | ||
40 | add \re, \ra, #8192 @ only necessary for 8k | ||
41 | 1001: ldr \rd, [\ra], #DCACHELINESIZE | ||
42 | teq \re, \ra | ||
43 | bne 1001b | ||
44 | #ifdef FLUSH_BASE_MINICACHE | ||
45 | add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE | ||
46 | add \re, \ra, #512 @ only 512 bytes | ||
47 | 1002: ldr \rd, [\ra], #DCACHELINESIZE | ||
48 | teq \re, \ra | ||
49 | bne 1002b | ||
50 | #endif | ||
51 | .endm | ||
52 | |||
53 | .data | ||
54 | flush_base: | ||
55 | .long FLUSH_BASE | ||
56 | .text | ||
57 | 33 | ||
58 | __INIT | 34 | __INIT |
59 | 35 | ||
@@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin) | |||
79 | stmfd sp!, {lr} | 55 | stmfd sp!, {lr} |
80 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | 56 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE |
81 | msr cpsr_c, ip | 57 | msr cpsr_c, ip |
82 | flush_1100_dcache r0, r1, r2 @ clean caches | 58 | bl v4wb_flush_kern_cache_all |
83 | mov r0, #0 | 59 | mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching |
84 | mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching | ||
85 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | 60 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
86 | bic r0, r0, #0x1000 @ ...i............ | 61 | bic r0, r0, #0x1000 @ ...i............ |
87 | bic r0, r0, #0x000e @ ............wca. | 62 | bic r0, r0, #0x000e @ ............wca. |
@@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area) | |||
167 | */ | 142 | */ |
168 | .align 5 | 143 | .align 5 |
169 | ENTRY(cpu_sa1100_switch_mm) | 144 | ENTRY(cpu_sa1100_switch_mm) |
170 | flush_1100_dcache r3, ip, r1 | 145 | str lr, [sp, #-4]! |
171 | mov ip, #0 | 146 | bl v4wb_flush_kern_cache_all @ clears IP |
172 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
173 | mcr p15, 0, ip, c9, c0, 0 @ invalidate RB | 147 | mcr p15, 0, ip, c9, c0, 0 @ invalidate RB |
174 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
175 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | 148 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
176 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | 149 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
177 | mov pc, lr | 150 | ldr pc, [sp], #4 |
178 | 151 | ||
179 | /* | 152 | /* |
180 | * cpu_sa1100_set_pte(ptep, pte) | 153 | * cpu_sa1100_set_pte(ptep, pte) |