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-rw-r--r--arch/arm/mm/proc-sa110.S11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a2dd5ae1077d..5a760a2c629c 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-sa110.S 2 * linux/arch/arm/mm/proc-sa110.S
3 * 3 *
4 * Copyright (C) 1997-2002 Russell King 4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -67,7 +68,9 @@ ENTRY(cpu_sa110_reset)
67 mov ip, #0 68 mov ip, #0
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71#ifdef CONFIG_MMU
70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73#endif
71 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
72 bic ip, ip, #0x000f @ ............wcam 75 bic ip, ip, #0x000f @ ............wcam
73 bic ip, ip, #0x1100 @ ...i...s........ 76 bic ip, ip, #0x1100 @ ...i...s........
@@ -130,11 +133,15 @@ ENTRY(cpu_sa110_dcache_clean_area)
130 */ 133 */
131 .align 5 134 .align 5
132ENTRY(cpu_sa110_switch_mm) 135ENTRY(cpu_sa110_switch_mm)
136#ifdef CONFIG_MMU
133 str lr, [sp, #-4]! 137 str lr, [sp, #-4]!
134 bl v4wb_flush_kern_cache_all @ clears IP 138 bl v4wb_flush_kern_cache_all @ clears IP
135 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 139 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
136 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 140 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
137 ldr pc, [sp], #4 141 ldr pc, [sp], #4
142#else
143 mov pc, lr
144#endif
138 145
139/* 146/*
140 * cpu_sa110_set_pte(ptep, pte) 147 * cpu_sa110_set_pte(ptep, pte)
@@ -143,6 +150,7 @@ ENTRY(cpu_sa110_switch_mm)
143 */ 150 */
144 .align 5 151 .align 5
145ENTRY(cpu_sa110_set_pte) 152ENTRY(cpu_sa110_set_pte)
153#ifdef CONFIG_MMU
146 str r1, [r0], #-2048 @ linux version 154 str r1, [r0], #-2048 @ linux version
147 155
148 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 156 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -164,6 +172,7 @@ ENTRY(cpu_sa110_set_pte)
164 mov r0, r0 172 mov r0, r0
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 173 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB 174 mcr p15, 0, r0, c7, c10, 4 @ drain WB
175#endif
167 mov pc, lr 176 mov pc, lr
168 177
169 __INIT 178 __INIT
@@ -173,7 +182,9 @@ __sa110_setup:
173 mov r10, #0 182 mov r10, #0
174 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 183 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
175 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 184 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
185#ifdef CONFIG_MMU
176 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif
177 mrc p15, 0, r0, c1, c0 @ get control register v4 188 mrc p15, 0, r0, c1, c0 @ get control register v4
178 ldr r5, sa110_cr1_clear 189 ldr r5, sa110_cr1_clear
179 bic r0, r0, r5 190 bic r0, r0, r5