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-rw-r--r--arch/arm/mm/proc-feroceon.S7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e632343849..b304d0104a4e 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
75 * cpu_feroceon_proc_fin() 75 * cpu_feroceon_proc_fin()
76 */ 76 */
77ENTRY(cpu_feroceon_proc_fin) 77ENTRY(cpu_feroceon_proc_fin)
78 stmfd sp!, {lr}
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
80 msr cpsr_c, ip
81 bl feroceon_flush_kern_cache_all
82
83#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 78#if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 79 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
85 mov r0, #0 80 mov r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
91 bic r0, r0, #0x1000 @ ...i............ 86 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca. 87 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
94 ldmfd sp!, {pc} 89 mov pc, lr
95 90
96/* 91/*
97 * cpu_feroceon_reset(loc) 92 * cpu_feroceon_reset(loc)