diff options
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
-rw-r--r-- | arch/arm/mm/proc-arm926.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 5b80b6bdd0cb..194ef48968e6 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
@@ -105,9 +105,13 @@ ENTRY(cpu_arm926_do_idle) | |||
105 | mrc p15, 0, r1, c1, c0, 0 @ Read control register | 105 | mrc p15, 0, r1, c1, c0, 0 @ Read control register |
106 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | 106 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer |
107 | bic r2, r1, #1 << 12 | 107 | bic r2, r1, #1 << 12 |
108 | mrs r3, cpsr @ Disable FIQs while Icache | ||
109 | orr ip, r3, #PSR_F_BIT @ is disabled | ||
110 | msr cpsr_c, ip | ||
108 | mcr p15, 0, r2, c1, c0, 0 @ Disable I cache | 111 | mcr p15, 0, r2, c1, c0, 0 @ Disable I cache |
109 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | 112 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt |
110 | mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable | 113 | mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable |
114 | msr cpsr_c, r3 @ Restore FIQ state | ||
111 | mov pc, lr | 115 | mov pc, lr |
112 | 116 | ||
113 | /* | 117 | /* |