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-rw-r--r--arch/arm/mm/proc-arm925.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index cb53435a85ae..8deb5bde58e4 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -251,15 +251,16 @@ ENTRY(arm925_coherent_user_range)
251 mov pc, lr 251 mov pc, lr
252 252
253/* 253/*
254 * flush_kern_dcache_page(void *page) 254 * flush_kern_dcache_area(void *addr, size_t size)
255 * 255 *
256 * Ensure no D cache aliasing occurs, either with itself or 256 * Ensure no D cache aliasing occurs, either with itself or
257 * the I cache 257 * the I cache
258 * 258 *
259 * - addr - page aligned address 259 * - addr - kernel address
260 * - size - region size
260 */ 261 */
261ENTRY(arm925_flush_kern_dcache_page) 262ENTRY(arm925_flush_kern_dcache_area)
262 add r1, r0, #PAGE_SZ 263 add r1, r0, r1
2631: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2641: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
264 add r0, r0, #CACHE_DLINESIZE 265 add r0, r0, #CACHE_DLINESIZE
265 cmp r0, r1 266 cmp r0, r1
@@ -346,7 +347,7 @@ ENTRY(arm925_cache_fns)
346 .long arm925_flush_user_cache_range 347 .long arm925_flush_user_cache_range
347 .long arm925_coherent_kern_range 348 .long arm925_coherent_kern_range
348 .long arm925_coherent_user_range 349 .long arm925_coherent_user_range
349 .long arm925_flush_kern_dcache_page 350 .long arm925_flush_kern_dcache_area
350 .long arm925_dma_inv_range 351 .long arm925_dma_inv_range
351 .long arm925_dma_clean_range 352 .long arm925_dma_clean_range
352 .long arm925_dma_flush_range 353 .long arm925_dma_flush_range