diff options
Diffstat (limited to 'arch/arm/mm/proc-arm720.S')
-rw-r--r-- | arch/arm/mm/proc-arm720.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 26f00ee2ad9a..86102467d37f 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S | |||
@@ -4,6 +4,7 @@ | |||
4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) |
5 | * Rob Scott (rscott@mtrob.fdns.net) | 5 | * Rob Scott (rscott@mtrob.fdns.net) |
6 | * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. | 6 | * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. |
7 | * hacked for non-paged-MM by Hyok S. Choi, 2004. | ||
7 | * | 8 | * |
8 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 10 | * it under the terms of the GNU General Public License as published by |
@@ -29,6 +30,7 @@ | |||
29 | * out of 'proc-arm6,7.S' per RMK discussion | 30 | * out of 'proc-arm6,7.S' per RMK discussion |
30 | * 07-25-2000 SJH Added idle function. | 31 | * 07-25-2000 SJH Added idle function. |
31 | * 08-25-2000 DBS Updated for integration of ARM Ltd version. | 32 | * 08-25-2000 DBS Updated for integration of ARM Ltd version. |
33 | * 04-20-2004 HSC modified for non-paged memory management mode. | ||
32 | */ | 34 | */ |
33 | #include <linux/linkage.h> | 35 | #include <linux/linkage.h> |
34 | #include <linux/init.h> | 36 | #include <linux/init.h> |
@@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle) | |||
75 | * the new. | 77 | * the new. |
76 | */ | 78 | */ |
77 | ENTRY(cpu_arm720_switch_mm) | 79 | ENTRY(cpu_arm720_switch_mm) |
80 | #ifdef CONFIG_MMU | ||
78 | mov r1, #0 | 81 | mov r1, #0 |
79 | mcr p15, 0, r1, c7, c7, 0 @ invalidate cache | 82 | mcr p15, 0, r1, c7, c7, 0 @ invalidate cache |
80 | mcr p15, 0, r0, c2, c0, 0 @ update page table ptr | 83 | mcr p15, 0, r0, c2, c0, 0 @ update page table ptr |
81 | mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) | 84 | mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) |
85 | #endif | ||
82 | mov pc, lr | 86 | mov pc, lr |
83 | 87 | ||
84 | /* | 88 | /* |
@@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm) | |||
89 | */ | 93 | */ |
90 | .align 5 | 94 | .align 5 |
91 | ENTRY(cpu_arm720_set_pte) | 95 | ENTRY(cpu_arm720_set_pte) |
96 | #ifdef CONFIG_MMU | ||
92 | str r1, [r0], #-2048 @ linux version | 97 | str r1, [r0], #-2048 @ linux version |
93 | 98 | ||
94 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 99 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY |
@@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte) | |||
107 | movne r2, #0 | 112 | movne r2, #0 |
108 | 113 | ||
109 | str r2, [r0] @ hardware version | 114 | str r2, [r0] @ hardware version |
115 | #endif | ||
110 | mov pc, lr | 116 | mov pc, lr |
111 | 117 | ||
112 | /* | 118 | /* |
@@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte) | |||
117 | ENTRY(cpu_arm720_reset) | 123 | ENTRY(cpu_arm720_reset) |
118 | mov ip, #0 | 124 | mov ip, #0 |
119 | mcr p15, 0, ip, c7, c7, 0 @ invalidate cache | 125 | mcr p15, 0, ip, c7, c7, 0 @ invalidate cache |
126 | #ifdef CONFIG_MMU | ||
120 | mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) | 127 | mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) |
128 | #endif | ||
121 | mrc p15, 0, ip, c1, c0, 0 @ get ctrl register | 129 | mrc p15, 0, ip, c1, c0, 0 @ get ctrl register |
122 | bic ip, ip, #0x000f @ ............wcam | 130 | bic ip, ip, #0x000f @ ............wcam |
123 | bic ip, ip, #0x2100 @ ..v....s........ | 131 | bic ip, ip, #0x2100 @ ..v....s........ |
@@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset) | |||
130 | __arm710_setup: | 138 | __arm710_setup: |
131 | mov r0, #0 | 139 | mov r0, #0 |
132 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches | 140 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches |
141 | #ifdef CONFIG_MMU | ||
133 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) | 142 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
143 | #endif | ||
134 | mrc p15, 0, r0, c1, c0 @ get control register | 144 | mrc p15, 0, r0, c1, c0 @ get control register |
135 | ldr r5, arm710_cr1_clear | 145 | ldr r5, arm710_cr1_clear |
136 | bic r0, r0, r5 | 146 | bic r0, r0, r5 |
@@ -156,7 +166,9 @@ arm710_cr1_set: | |||
156 | __arm720_setup: | 166 | __arm720_setup: |
157 | mov r0, #0 | 167 | mov r0, #0 |
158 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches | 168 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches |
169 | #ifdef CONFIG_MMU | ||
159 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) | 170 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
171 | #endif | ||
160 | mrc p15, 0, r0, c1, c0 @ get control register | 172 | mrc p15, 0, r0, c1, c0 @ get control register |
161 | ldr r5, arm720_cr1_clear | 173 | ldr r5, arm720_cr1_clear |
162 | bic r0, r0, r5 | 174 | bic r0, r0, r5 |