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-rw-r--r--arch/arm/mm/proc-arm6_7.S27
1 files changed, 6 insertions, 21 deletions
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index c371fc87776e..80d6e1de069a 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,11 +15,13 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
18#include <asm/elf.h> 18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable-hwdef.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
22 22
23#include "proc-macros.S"
24
23ENTRY(cpu_arm6_dcache_clean_area) 25ENTRY(cpu_arm6_dcache_clean_area)
24ENTRY(cpu_arm7_dcache_clean_area) 26ENTRY(cpu_arm7_dcache_clean_area)
25 mov pc, lr 27 mov pc, lr
@@ -214,30 +216,13 @@ ENTRY(cpu_arm7_switch_mm)
214 * : r1 = value to set 216 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache 217 * Purpose : Set a PTE and flush it out of any WB cache
216 */ 218 */
217 .align 5 219 .align 5
218ENTRY(cpu_arm6_set_pte_ext) 220ENTRY(cpu_arm6_set_pte_ext)
219ENTRY(cpu_arm7_set_pte_ext) 221ENTRY(cpu_arm7_set_pte_ext)
220#ifdef CONFIG_MMU 222#ifdef CONFIG_MMU
221 str r1, [r0], #-2048 @ linux version 223 armv3_set_pte_ext wc_disable=0
222
223 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
224
225 bic r2, r1, #PTE_SMALL_AP_MASK
226 bic r2, r2, #PTE_TYPE_MASK
227 orr r2, r2, #PTE_TYPE_SMALL
228
229 tst r1, #L_PTE_USER @ User?
230 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
231
232 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
233 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
234
235 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
236 movne r2, #0
237
238 str r2, [r0] @ hardware version
239#endif /* CONFIG_MMU */ 224#endif /* CONFIG_MMU */
240 mov pc, lr 225 mov pc, lr
241 226
242/* 227/*
243 * Function: _arm6_7_reset 228 * Function: _arm6_7_reset