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-rw-r--r--arch/arm/mm/proc-arm1026.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3b59f0d67139..96aedb10fcc4 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -208,17 +208,18 @@ ENTRY(arm1026_coherent_user_range)
208 mov pc, lr 208 mov pc, lr
209 209
210/* 210/*
211 * flush_kern_dcache_page(void *page) 211 * flush_kern_dcache_area(void *addr, size_t size)
212 * 212 *
213 * Ensure no D cache aliasing occurs, either with itself or 213 * Ensure no D cache aliasing occurs, either with itself or
214 * the I cache 214 * the I cache
215 * 215 *
216 * - page - page aligned address 216 * - addr - kernel address
217 * - size - region size
217 */ 218 */
218ENTRY(arm1026_flush_kern_dcache_page) 219ENTRY(arm1026_flush_kern_dcache_area)
219 mov ip, #0 220 mov ip, #0
220#ifndef CONFIG_CPU_DCACHE_DISABLE 221#ifndef CONFIG_CPU_DCACHE_DISABLE
221 add r1, r0, #PAGE_SZ 222 add r1, r0, r1
2221: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2231: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
223 add r0, r0, #CACHE_DLINESIZE 224 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1 225 cmp r0, r1
@@ -304,7 +305,7 @@ ENTRY(arm1026_cache_fns)
304 .long arm1026_flush_user_cache_range 305 .long arm1026_flush_user_cache_range
305 .long arm1026_coherent_kern_range 306 .long arm1026_coherent_kern_range
306 .long arm1026_coherent_user_range 307 .long arm1026_coherent_user_range
307 .long arm1026_flush_kern_dcache_page 308 .long arm1026_flush_kern_dcache_area
308 .long arm1026_dma_inv_range 309 .long arm1026_dma_inv_range
309 .long arm1026_dma_clean_range 310 .long arm1026_dma_clean_range
310 .long arm1026_dma_flush_range 311 .long arm1026_dma_flush_range