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-rw-r--r--arch/arm/mm/proc-arm1022.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8eb72d75a8b6..20a5b1b31a70 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -214,17 +214,18 @@ ENTRY(arm1022_coherent_user_range)
214 mov pc, lr 214 mov pc, lr
215 215
216/* 216/*
217 * flush_kern_dcache_page(void *page) 217 * flush_kern_dcache_area(void *addr, size_t size)
218 * 218 *
219 * Ensure no D cache aliasing occurs, either with itself or 219 * Ensure no D cache aliasing occurs, either with itself or
220 * the I cache 220 * the I cache
221 * 221 *
222 * - page - page aligned address 222 * - addr - kernel address
223 * - size - region size
223 */ 224 */
224ENTRY(arm1022_flush_kern_dcache_page) 225ENTRY(arm1022_flush_kern_dcache_area)
225 mov ip, #0 226 mov ip, #0
226#ifndef CONFIG_CPU_DCACHE_DISABLE 227#ifndef CONFIG_CPU_DCACHE_DISABLE
227 add r1, r0, #PAGE_SZ 228 add r1, r0, r1
2281: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2291: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
229 add r0, r0, #CACHE_DLINESIZE 230 add r0, r0, #CACHE_DLINESIZE
230 cmp r0, r1 231 cmp r0, r1
@@ -310,7 +311,7 @@ ENTRY(arm1022_cache_fns)
310 .long arm1022_flush_user_cache_range 311 .long arm1022_flush_user_cache_range
311 .long arm1022_coherent_kern_range 312 .long arm1022_coherent_kern_range
312 .long arm1022_coherent_user_range 313 .long arm1022_coherent_user_range
313 .long arm1022_flush_kern_dcache_page 314 .long arm1022_flush_kern_dcache_area
314 .long arm1022_dma_inv_range 315 .long arm1022_dma_inv_range
315 .long arm1022_dma_clean_range 316 .long arm1022_dma_clean_range
316 .long arm1022_dma_flush_range 317 .long arm1022_dma_flush_range