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-rw-r--r--arch/arm/mm/proc-arm1020e.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index be6d081ff2b7..bcd5ee022e00 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset)
101 mov ip, #0 102 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107#endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam 109 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........ 110 bic ip, ip, #0x1100 @ ...i...s........
@@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
344 */ 347 */
345 .align 5 348 .align 5
346ENTRY(cpu_arm1020e_switch_mm) 349ENTRY(cpu_arm1020e_switch_mm)
350#ifdef CONFIG_MMU
347#ifndef CONFIG_CPU_DCACHE_DISABLE 351#ifndef CONFIG_CPU_DCACHE_DISABLE
348 mcr p15, 0, r3, c7, c10, 4 352 mcr p15, 0, r3, c7, c10, 4
349 mov r1, #0xF @ 16 segments 353 mov r1, #0xF @ 16 segments
@@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm)
367 mcr p15, 0, r1, c7, c10, 4 @ drain WB 371 mcr p15, 0, r1, c7, c10, 4 @ drain WB
368 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 372 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
369 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 373 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
374#endif
370 mov pc, lr 375 mov pc, lr
371 376
372/* 377/*
@@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
376 */ 381 */
377 .align 5 382 .align 5
378ENTRY(cpu_arm1020e_set_pte) 383ENTRY(cpu_arm1020e_set_pte)
384#ifdef CONFIG_MMU
379 str r1, [r0], #-2048 @ linux version 385 str r1, [r0], #-2048 @ linux version
380 386
381 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 387 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte)
403#ifndef CONFIG_CPU_DCACHE_DISABLE 409#ifndef CONFIG_CPU_DCACHE_DISABLE
404 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
405#endif 411#endif
412#endif /* CONFIG_MMU */
406 mov pc, lr 413 mov pc, lr
407 414
408 __INIT 415 __INIT
@@ -412,7 +419,9 @@ __arm1020e_setup:
412 mov r0, #0 419 mov r0, #0
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
422#ifdef CONFIG_MMU
415 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424#endif
416 mrc p15, 0, r0, c1, c0 @ get control register v4 425 mrc p15, 0, r0, c1, c0 @ get control register v4
417 ldr r5, arm1020e_cr1_clear 426 ldr r5, arm1020e_cr1_clear
418 bic r0, r0, r5 427 bic r0, r0, r5