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-rw-r--r--arch/arm/mm/proc-arm1020e.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 7453b75dcea5..41fe25d234f5 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -225,17 +225,18 @@ ENTRY(arm1020e_coherent_user_range)
225 mov pc, lr 225 mov pc, lr
226 226
227/* 227/*
228 * flush_kern_dcache_page(void *page) 228 * flush_kern_dcache_area(void *addr, size_t size)
229 * 229 *
230 * Ensure no D cache aliasing occurs, either with itself or 230 * Ensure no D cache aliasing occurs, either with itself or
231 * the I cache 231 * the I cache
232 * 232 *
233 * - page - page aligned address 233 * - addr - kernel address
234 * - size - region size
234 */ 235 */
235ENTRY(arm1020e_flush_kern_dcache_page) 236ENTRY(arm1020e_flush_kern_dcache_area)
236 mov ip, #0 237 mov ip, #0
237#ifndef CONFIG_CPU_DCACHE_DISABLE 238#ifndef CONFIG_CPU_DCACHE_DISABLE
238 add r1, r0, #PAGE_SZ 239 add r1, r0, r1
2391: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2401: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 add r0, r0, #CACHE_DLINESIZE 241 add r0, r0, #CACHE_DLINESIZE
241 cmp r0, r1 242 cmp r0, r1
@@ -321,7 +322,7 @@ ENTRY(arm1020e_cache_fns)
321 .long arm1020e_flush_user_cache_range 322 .long arm1020e_flush_user_cache_range
322 .long arm1020e_coherent_kern_range 323 .long arm1020e_coherent_kern_range
323 .long arm1020e_coherent_user_range 324 .long arm1020e_coherent_user_range
324 .long arm1020e_flush_kern_dcache_page 325 .long arm1020e_flush_kern_dcache_area
325 .long arm1020e_dma_inv_range 326 .long arm1020e_dma_inv_range
326 .long arm1020e_dma_clean_range 327 .long arm1020e_dma_clean_range
327 .long arm1020e_dma_flush_range 328 .long arm1020e_dma_flush_range