aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-arm1020e.S
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mm/proc-arm1020e.S')
-rw-r--r--arch/arm/mm/proc-arm1020e.S43
1 files changed, 34 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 7453b75dcea5..d27829805609 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -225,17 +225,18 @@ ENTRY(arm1020e_coherent_user_range)
225 mov pc, lr 225 mov pc, lr
226 226
227/* 227/*
228 * flush_kern_dcache_page(void *page) 228 * flush_kern_dcache_area(void *addr, size_t size)
229 * 229 *
230 * Ensure no D cache aliasing occurs, either with itself or 230 * Ensure no D cache aliasing occurs, either with itself or
231 * the I cache 231 * the I cache
232 * 232 *
233 * - page - page aligned address 233 * - addr - kernel address
234 * - size - region size
234 */ 235 */
235ENTRY(arm1020e_flush_kern_dcache_page) 236ENTRY(arm1020e_flush_kern_dcache_area)
236 mov ip, #0 237 mov ip, #0
237#ifndef CONFIG_CPU_DCACHE_DISABLE 238#ifndef CONFIG_CPU_DCACHE_DISABLE
238 add r1, r0, #PAGE_SZ 239 add r1, r0, r1
2391: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2401: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 add r0, r0, #CACHE_DLINESIZE 241 add r0, r0, #CACHE_DLINESIZE
241 cmp r0, r1 242 cmp r0, r1
@@ -257,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_page)
257 * 258 *
258 * (same as v4wb) 259 * (same as v4wb)
259 */ 260 */
260ENTRY(arm1020e_dma_inv_range) 261arm1020e_dma_inv_range:
261 mov ip, #0 262 mov ip, #0
262#ifndef CONFIG_CPU_DCACHE_DISABLE 263#ifndef CONFIG_CPU_DCACHE_DISABLE
263 tst r0, #CACHE_DLINESIZE - 1 264 tst r0, #CACHE_DLINESIZE - 1
@@ -283,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range)
283 * 284 *
284 * (same as v4wb) 285 * (same as v4wb)
285 */ 286 */
286ENTRY(arm1020e_dma_clean_range) 287arm1020e_dma_clean_range:
287 mov ip, #0 288 mov ip, #0
288#ifndef CONFIG_CPU_DCACHE_DISABLE 289#ifndef CONFIG_CPU_DCACHE_DISABLE
289 bic r0, r0, #CACHE_DLINESIZE - 1 290 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -315,15 +316,39 @@ ENTRY(arm1020e_dma_flush_range)
315 mcr p15, 0, ip, c7, c10, 4 @ drain WB 316 mcr p15, 0, ip, c7, c10, 4 @ drain WB
316 mov pc, lr 317 mov pc, lr
317 318
319/*
320 * dma_map_area(start, size, dir)
321 * - start - kernel virtual start address
322 * - size - size of region
323 * - dir - DMA direction
324 */
325ENTRY(arm1020e_dma_map_area)
326 add r1, r1, r0
327 cmp r2, #DMA_TO_DEVICE
328 beq arm1020e_dma_clean_range
329 bcs arm1020e_dma_inv_range
330 b arm1020e_dma_flush_range
331ENDPROC(arm1020e_dma_map_area)
332
333/*
334 * dma_unmap_area(start, size, dir)
335 * - start - kernel virtual start address
336 * - size - size of region
337 * - dir - DMA direction
338 */
339ENTRY(arm1020e_dma_unmap_area)
340 mov pc, lr
341ENDPROC(arm1020e_dma_unmap_area)
342
318ENTRY(arm1020e_cache_fns) 343ENTRY(arm1020e_cache_fns)
319 .long arm1020e_flush_kern_cache_all 344 .long arm1020e_flush_kern_cache_all
320 .long arm1020e_flush_user_cache_all 345 .long arm1020e_flush_user_cache_all
321 .long arm1020e_flush_user_cache_range 346 .long arm1020e_flush_user_cache_range
322 .long arm1020e_coherent_kern_range 347 .long arm1020e_coherent_kern_range
323 .long arm1020e_coherent_user_range 348 .long arm1020e_coherent_user_range
324 .long arm1020e_flush_kern_dcache_page 349 .long arm1020e_flush_kern_dcache_area
325 .long arm1020e_dma_inv_range 350 .long arm1020e_dma_map_area
326 .long arm1020e_dma_clean_range 351 .long arm1020e_dma_unmap_area
327 .long arm1020e_dma_flush_range 352 .long arm1020e_dma_flush_range
328 353
329 .align 5 354 .align 5