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-rw-r--r--arch/arm/mm/proc-arm1020.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index d9fb4b98c49f..8012e24282b2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -231,17 +231,18 @@ ENTRY(arm1020_coherent_user_range)
231 mov pc, lr 231 mov pc, lr
232 232
233/* 233/*
234 * flush_kern_dcache_page(void *page) 234 * flush_kern_dcache_area(void *addr, size_t size)
235 * 235 *
236 * Ensure no D cache aliasing occurs, either with itself or 236 * Ensure no D cache aliasing occurs, either with itself or
237 * the I cache 237 * the I cache
238 * 238 *
239 * - page - page aligned address 239 * - addr - kernel address
240 * - size - region size
240 */ 241 */
241ENTRY(arm1020_flush_kern_dcache_page) 242ENTRY(arm1020_flush_kern_dcache_area)
242 mov ip, #0 243 mov ip, #0
243#ifndef CONFIG_CPU_DCACHE_DISABLE 244#ifndef CONFIG_CPU_DCACHE_DISABLE
244 add r1, r0, #PAGE_SZ 245 add r1, r0, r1
2451: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2461: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
246 mcr p15, 0, ip, c7, c10, 4 @ drain WB 247 mcr p15, 0, ip, c7, c10, 4 @ drain WB
247 add r0, r0, #CACHE_DLINESIZE 248 add r0, r0, #CACHE_DLINESIZE
@@ -335,7 +336,7 @@ ENTRY(arm1020_cache_fns)
335 .long arm1020_flush_user_cache_range 336 .long arm1020_flush_user_cache_range
336 .long arm1020_coherent_kern_range 337 .long arm1020_coherent_kern_range
337 .long arm1020_coherent_user_range 338 .long arm1020_coherent_user_range
338 .long arm1020_flush_kern_dcache_page 339 .long arm1020_flush_kern_dcache_area
339 .long arm1020_dma_inv_range 340 .long arm1020_dma_inv_range
340 .long arm1020_dma_clean_range 341 .long arm1020_dma_clean_range
341 .long arm1020_dma_flush_range 342 .long arm1020_dma_flush_range