diff options
Diffstat (limited to 'arch/arm/mm/context.c')
| -rw-r--r-- | arch/arm/mm/context.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 9da43a0fdcdf..fc84fcc74380 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
| @@ -14,7 +14,8 @@ | |||
| 14 | #include <asm/mmu_context.h> | 14 | #include <asm/mmu_context.h> |
| 15 | #include <asm/tlbflush.h> | 15 | #include <asm/tlbflush.h> |
| 16 | 16 | ||
| 17 | unsigned int cpu_last_asid = { 1 << ASID_BITS }; | 17 | static DEFINE_SPINLOCK(cpu_asid_lock); |
| 18 | unsigned int cpu_last_asid = ASID_FIRST_VERSION; | ||
| 18 | 19 | ||
| 19 | /* | 20 | /* |
| 20 | * We fork()ed a process, and we need a new context for the child | 21 | * We fork()ed a process, and we need a new context for the child |
| @@ -31,15 +32,16 @@ void __new_context(struct mm_struct *mm) | |||
| 31 | { | 32 | { |
| 32 | unsigned int asid; | 33 | unsigned int asid; |
| 33 | 34 | ||
| 35 | spin_lock(&cpu_asid_lock); | ||
| 34 | asid = ++cpu_last_asid; | 36 | asid = ++cpu_last_asid; |
| 35 | if (asid == 0) | 37 | if (asid == 0) |
| 36 | asid = cpu_last_asid = 1 << ASID_BITS; | 38 | asid = cpu_last_asid = ASID_FIRST_VERSION; |
| 37 | 39 | ||
| 38 | /* | 40 | /* |
| 39 | * If we've used up all our ASIDs, we need | 41 | * If we've used up all our ASIDs, we need |
| 40 | * to start a new version and flush the TLB. | 42 | * to start a new version and flush the TLB. |
| 41 | */ | 43 | */ |
| 42 | if ((asid & ~ASID_MASK) == 0) { | 44 | if (unlikely((asid & ~ASID_MASK) == 0)) { |
| 43 | asid = ++cpu_last_asid; | 45 | asid = ++cpu_last_asid; |
| 44 | /* set the reserved ASID before flushing the TLB */ | 46 | /* set the reserved ASID before flushing the TLB */ |
| 45 | asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n" | 47 | asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n" |
| @@ -47,7 +49,16 @@ void __new_context(struct mm_struct *mm) | |||
| 47 | : "r" (0)); | 49 | : "r" (0)); |
| 48 | isb(); | 50 | isb(); |
| 49 | flush_tlb_all(); | 51 | flush_tlb_all(); |
| 52 | if (icache_is_vivt_asid_tagged()) { | ||
| 53 | asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" | ||
| 54 | "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n" | ||
| 55 | : | ||
| 56 | : "r" (0)); | ||
| 57 | dsb(); | ||
| 58 | } | ||
| 50 | } | 59 | } |
| 60 | spin_unlock(&cpu_asid_lock); | ||
| 51 | 61 | ||
| 62 | mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id()); | ||
| 52 | mm->context.id = asid; | 63 | mm->context.id = asid; |
| 53 | } | 64 | } |
