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-rw-r--r--arch/arm/mm/context.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 8bfae964b133..b6c776ae4039 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
24 24
25/* 25/*
26 * We fork()ed a process, and we need a new context for the child 26 * We fork()ed a process, and we need a new context for the child
27 * to run in. 27 * to run in. We reserve version 0 for initial tasks so we will
28 * always allocate an ASID. The ASID 0 is reserved for the TTBR
29 * register changing sequence.
28 */ 30 */
29void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 31void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
30{ 32{
@@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
34 36
35static void flush_context(void) 37static void flush_context(void)
36{ 38{
37 u32 ttb; 39 /* set the reserved ASID before flushing the TLB */
38 /* Copy TTBR1 into TTBR0 */ 40 asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0));
39 asm volatile("mrc p15, 0, %0, c2, c0, 1\n"
40 "mcr p15, 0, %0, c2, c0, 0"
41 : "=r" (ttb));
42 isb(); 41 isb();
43 local_flush_tlb_all(); 42 local_flush_tlb_all();
44 if (icache_is_vivt_asid_tagged()) { 43 if (icache_is_vivt_asid_tagged()) {