diff options
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 15451ee4acc8..515b00064da8 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
| @@ -92,6 +92,14 @@ ENTRY(v7_flush_dcache_louis) | |||
| 92 | mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr | 92 | mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr |
| 93 | ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr | 93 | ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr |
| 94 | ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr | 94 | ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr |
| 95 | #ifdef CONFIG_ARM_ERRATA_643719 | ||
| 96 | ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register | ||
| 97 | ALT_UP(moveq pc, lr) @ LoUU is zero, so nothing to do | ||
| 98 | ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? | ||
| 99 | biceq r2, r2, #0x0000000f @ clear minor revision number | ||
| 100 | teqeq r2, r1 @ test for errata affected core and if so... | ||
| 101 | orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') | ||
| 102 | #endif | ||
| 95 | ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 | 103 | ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 |
| 96 | ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 | 104 | ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 |
| 97 | moveq pc, lr @ return if level == 0 | 105 | moveq pc, lr @ return if level == 0 |