diff options
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r-- | arch/arm/mm/cache-v7.S | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index be93ff02a98d..bda0ec31a4e2 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
@@ -21,7 +21,7 @@ | |||
21 | * | 21 | * |
22 | * Flush the whole D-cache. | 22 | * Flush the whole D-cache. |
23 | * | 23 | * |
24 | * Corrupted registers: r0-r5, r7, r9-r11 | 24 | * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) |
25 | * | 25 | * |
26 | * - mm - mm_struct describing address space | 26 | * - mm - mm_struct describing address space |
27 | */ | 27 | */ |
@@ -51,8 +51,12 @@ loop1: | |||
51 | loop2: | 51 | loop2: |
52 | mov r9, r4 @ create working copy of max way size | 52 | mov r9, r4 @ create working copy of max way size |
53 | loop3: | 53 | loop3: |
54 | orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 | 54 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
55 | orr r11, r11, r7, lsl r2 @ factor index number into r11 | 55 | THUMB( lsl r6, r9, r5 ) |
56 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 | ||
57 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 | ||
58 | THUMB( lsl r6, r7, r2 ) | ||
59 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 | ||
56 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way | 60 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
57 | subs r9, r9, #1 @ decrement the way | 61 | subs r9, r9, #1 @ decrement the way |
58 | bge loop3 | 62 | bge loop3 |
@@ -82,11 +86,13 @@ ENDPROC(v7_flush_dcache_all) | |||
82 | * | 86 | * |
83 | */ | 87 | */ |
84 | ENTRY(v7_flush_kern_cache_all) | 88 | ENTRY(v7_flush_kern_cache_all) |
85 | stmfd sp!, {r4-r5, r7, r9-r11, lr} | 89 | ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) |
90 | THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) | ||
86 | bl v7_flush_dcache_all | 91 | bl v7_flush_dcache_all |
87 | mov r0, #0 | 92 | mov r0, #0 |
88 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate | 93 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate |
89 | ldmfd sp!, {r4-r5, r7, r9-r11, lr} | 94 | ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) |
95 | THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) | ||
90 | mov pc, lr | 96 | mov pc, lr |
91 | ENDPROC(v7_flush_kern_cache_all) | 97 | ENDPROC(v7_flush_kern_cache_all) |
92 | 98 | ||