diff options
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r-- | arch/arm/mm/cache-v7.S | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index b966656d2c2d..a134d8a13d00 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
@@ -36,10 +36,10 @@ ENTRY(v7_invalidate_l1) | |||
36 | mcr p15, 2, r0, c0, c0, 0 | 36 | mcr p15, 2, r0, c0, c0, 0 |
37 | mrc p15, 1, r0, c0, c0, 0 | 37 | mrc p15, 1, r0, c0, c0, 0 |
38 | 38 | ||
39 | ldr r1, =0x7fff | 39 | movw r1, #0x7fff |
40 | and r2, r1, r0, lsr #13 | 40 | and r2, r1, r0, lsr #13 |
41 | 41 | ||
42 | ldr r1, =0x3ff | 42 | movw r1, #0x3ff |
43 | 43 | ||
44 | and r3, r1, r0, lsr #3 @ NumWays - 1 | 44 | and r3, r1, r0, lsr #3 @ NumWays - 1 |
45 | add r2, r2, #1 @ NumSets | 45 | add r2, r2, #1 @ NumSets |
@@ -90,21 +90,20 @@ ENDPROC(v7_flush_icache_all) | |||
90 | ENTRY(v7_flush_dcache_louis) | 90 | ENTRY(v7_flush_dcache_louis) |
91 | dmb @ ensure ordering with previous memory accesses | 91 | dmb @ ensure ordering with previous memory accesses |
92 | mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr | 92 | mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr |
93 | ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr | 93 | ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position |
94 | ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr | 94 | ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position |
95 | ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr | ||
96 | bne start_flush_levels @ LoU != 0, start flushing | ||
95 | #ifdef CONFIG_ARM_ERRATA_643719 | 97 | #ifdef CONFIG_ARM_ERRATA_643719 |
96 | ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register | 98 | ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register |
97 | ALT_UP(reteq lr) @ LoUU is zero, so nothing to do | 99 | ALT_UP( ret lr) @ LoUU is zero, so nothing to do |
98 | ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? | 100 | movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p? |
99 | biceq r2, r2, #0x0000000f @ clear minor revision number | 101 | movt r1, #:upper16:(0x410fc090 >> 4) |
100 | teqeq r2, r1 @ test for errata affected core and if so... | 102 | teq r1, r2, lsr #4 @ test for errata affected core and if so... |
101 | orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') | 103 | moveq r3, #1 << 1 @ fix LoUIS value |
104 | beq start_flush_levels @ start flushing cache levels | ||
102 | #endif | 105 | #endif |
103 | ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 | 106 | ret lr |
104 | ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 | ||
105 | reteq lr @ return if level == 0 | ||
106 | mov r10, #0 @ r10 (starting level) = 0 | ||
107 | b flush_levels @ start flushing cache levels | ||
108 | ENDPROC(v7_flush_dcache_louis) | 107 | ENDPROC(v7_flush_dcache_louis) |
109 | 108 | ||
110 | /* | 109 | /* |
@@ -119,9 +118,10 @@ ENDPROC(v7_flush_dcache_louis) | |||
119 | ENTRY(v7_flush_dcache_all) | 118 | ENTRY(v7_flush_dcache_all) |
120 | dmb @ ensure ordering with previous memory accesses | 119 | dmb @ ensure ordering with previous memory accesses |
121 | mrc p15, 1, r0, c0, c0, 1 @ read clidr | 120 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
122 | ands r3, r0, #0x7000000 @ extract loc from clidr | 121 | mov r3, r0, lsr #23 @ move LoC into position |
123 | mov r3, r3, lsr #23 @ left align loc bit field | 122 | ands r3, r3, #7 << 1 @ extract LoC*2 from clidr |
124 | beq finished @ if loc is 0, then no need to clean | 123 | beq finished @ if loc is 0, then no need to clean |
124 | start_flush_levels: | ||
125 | mov r10, #0 @ start clean at cache level 0 | 125 | mov r10, #0 @ start clean at cache level 0 |
126 | flush_levels: | 126 | flush_levels: |
127 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | 127 | add r2, r10, r10, lsr #1 @ work out 3x current cache level |
@@ -140,10 +140,10 @@ flush_levels: | |||
140 | #endif | 140 | #endif |
141 | and r2, r1, #7 @ extract the length of the cache lines | 141 | and r2, r1, #7 @ extract the length of the cache lines |
142 | add r2, r2, #4 @ add 4 (line length offset) | 142 | add r2, r2, #4 @ add 4 (line length offset) |
143 | ldr r4, =0x3ff | 143 | movw r4, #0x3ff |
144 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | 144 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size |
145 | clz r5, r4 @ find bit position of way size increment | 145 | clz r5, r4 @ find bit position of way size increment |
146 | ldr r7, =0x7fff | 146 | movw r7, #0x7fff |
147 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | 147 | ands r7, r7, r1, lsr #13 @ extract max number of the index size |
148 | loop1: | 148 | loop1: |
149 | mov r9, r7 @ create working copy of max index | 149 | mov r9, r7 @ create working copy of max index |