1 files changed, 2 insertions, 0 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d19c2bec2b1f..be93ff02a98d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -26,6 +26,7 @@
  *      - mm    - mm_struct describing address space
  */
 ENTRY(v7_flush_dcache_all)
+        dmb                                     @ ensure ordering with previous memory accesses
         mrc     p15, 1, r0, c0, c0, 1           @ read clidr
         ands    r3, r0, #0x7000000              @ extract loc from clidr
         mov     r3, r3, lsr #23                 @ left align loc bit field
@@ -64,6 +65,7 @@ skip:
 finished:
         mov     r10, #0                         @ swith back to cache level 0
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
+        dsb
         isb
         mov     pc, lr
 ENDPROC(v7_flush_dcache_all)