1 files changed, 7 insertions, 6 deletions

diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 11e5e5838bc5..a0982ce49007 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -13,6 +13,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/assembler.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
@@ -48,7 +49,7 @@
 ENTRY(v4wt_flush_icache_all)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mov     pc, lr
+        ret     lr
 ENDPROC(v4wt_flush_icache_all)
 
 /*
@@ -71,7 +72,7 @@ __flush_whole_cache:
         tst     r2, #VM_EXEC
         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
-        mov     pc, lr
+        ret     lr
 
 /*
  *      flush_user_cache_range(start, end, flags)
@@ -94,7 +95,7 @@ ENTRY(v4wt_flush_user_cache_range)
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
         blo     1b
-        mov     pc, lr
+        ret     lr
 
 /*
  *      coherent_kern_range(start, end)
@@ -126,7 +127,7 @@ ENTRY(v4wt_coherent_user_range)
         cmp     r0, r1
         blo     1b
         mov     r0, #0
-        mov     pc, lr
+        ret     lr
 
 /*
  *      flush_kern_dcache_area(void *addr, size_t size)
@@ -160,7 +161,7 @@ v4wt_dma_inv_range:
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
         blo     1b
-        mov     pc, lr
+        ret     lr
 
 /*
  *      dma_flush_range(start, end)
@@ -192,7 +193,7 @@ ENTRY(v4wt_dma_unmap_area)
  *      - dir   - DMA direction
  */
 ENTRY(v4wt_dma_map_area)
-        mov     pc, lr
+        ret     lr
 ENDPROC(v4wt_dma_unmap_area)
 ENDPROC(v4wt_dma_map_area)