1 files changed, 13 insertions, 1 deletions

diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 45c70312f43b..a7b276dbda11 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -34,13 +34,24 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  *
  * *** This needs benchmarking
  */
 #define CACHE_DLIMIT    16384
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4wt_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(v4wt_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -188,6 +199,7 @@ ENDPROC(v4wt_dma_map_area)
 
         .type   v4wt_cache_fns, #object
 ENTRY(v4wt_cache_fns)
+        .long   v4wt_flush_icache_all
         .long   v4wt_flush_kern_cache_all
         .long   v4wt_flush_user_cache_all
         .long   v4wt_flush_user_cache_range