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-rw-r--r--arch/arm/mm/cache-v4wb.S32
1 files changed, 28 insertions, 4 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 3dbedf1ec0e7..df8368afa102 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
173 * - start - virtual start address 173 * - start - virtual start address
174 * - end - virtual end address 174 * - end - virtual end address
175 */ 175 */
176ENTRY(v4wb_dma_inv_range) 176v4wb_dma_inv_range:
177 tst r0, #CACHE_DLINESIZE - 1 177 tst r0, #CACHE_DLINESIZE - 1
178 bic r0, r0, #CACHE_DLINESIZE - 1 178 bic r0, r0, #CACHE_DLINESIZE - 1
179 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 179 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range)
194 * - start - virtual start address 194 * - start - virtual start address
195 * - end - virtual end address 195 * - end - virtual end address
196 */ 196 */
197ENTRY(v4wb_dma_clean_range) 197v4wb_dma_clean_range:
198 bic r0, r0, #CACHE_DLINESIZE - 1 198 bic r0, r0, #CACHE_DLINESIZE - 1
1991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
200 add r0, r0, #CACHE_DLINESIZE 200 add r0, r0, #CACHE_DLINESIZE
@@ -216,6 +216,30 @@ ENTRY(v4wb_dma_clean_range)
216 .globl v4wb_dma_flush_range 216 .globl v4wb_dma_flush_range
217 .set v4wb_dma_flush_range, v4wb_coherent_kern_range 217 .set v4wb_dma_flush_range, v4wb_coherent_kern_range
218 218
219/*
220 * dma_map_area(start, size, dir)
221 * - start - kernel virtual start address
222 * - size - size of region
223 * - dir - DMA direction
224 */
225ENTRY(v4wb_dma_map_area)
226 add r1, r1, r0
227 cmp r2, #DMA_TO_DEVICE
228 beq v4wb_dma_clean_range
229 bcs v4wb_dma_inv_range
230 b v4wb_dma_flush_range
231ENDPROC(v4wb_dma_map_area)
232
233/*
234 * dma_unmap_area(start, size, dir)
235 * - start - kernel virtual start address
236 * - size - size of region
237 * - dir - DMA direction
238 */
239ENTRY(v4wb_dma_unmap_area)
240 mov pc, lr
241ENDPROC(v4wb_dma_unmap_area)
242
219 __INITDATA 243 __INITDATA
220 244
221 .type v4wb_cache_fns, #object 245 .type v4wb_cache_fns, #object
@@ -226,7 +250,7 @@ ENTRY(v4wb_cache_fns)
226 .long v4wb_coherent_kern_range 250 .long v4wb_coherent_kern_range
227 .long v4wb_coherent_user_range 251 .long v4wb_coherent_user_range
228 .long v4wb_flush_kern_dcache_area 252 .long v4wb_flush_kern_dcache_area
229 .long v4wb_dma_inv_range 253 .long v4wb_dma_map_area
230 .long v4wb_dma_clean_range 254 .long v4wb_dma_unmap_area
231 .long v4wb_dma_flush_range 255 .long v4wb_dma_flush_range
232 .size v4wb_cache_fns, . - v4wb_cache_fns 256 .size v4wb_cache_fns, . - v4wb_cache_fns