1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 4f2c14151ccb..8f1eeae340c8 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range)
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
        blo     1b
-        mov     ip, #0
+        mov     r0, #0
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 4f2c14151ccb..8f1eeae340c8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S
@@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range)
167	add r0, r0, #CACHE_DLINESIZE	167	add r0, r0, #CACHE_DLINESIZE
168	cmp r0, r1	168	cmp r0, r1
169	blo 1b	169	blo 1b
170	mov ip, #0	170	mov r0, #0
171	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache	171	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
172	mcr p15, 0, ip, c7, c10, 4 @ drain WB	172	mcr p15, 0, r0, c7, c10, 4 @ drain WB
173	mov pc, lr	173	mov pc, lr
174		174
175		175