diff options
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a53fd2aaa2f4..2a8e380501e8 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -32,6 +32,7 @@ static void __iomem *l2x0_base; | |||
32 | static DEFINE_RAW_SPINLOCK(l2x0_lock); | 32 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
33 | static u32 l2x0_way_mask; /* Bitmask of active ways */ | 33 | static u32 l2x0_way_mask; /* Bitmask of active ways */ |
34 | static u32 l2x0_size; | 34 | static u32 l2x0_size; |
35 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; | ||
35 | 36 | ||
36 | struct l2x0_regs l2x0_saved_regs; | 37 | struct l2x0_regs l2x0_saved_regs; |
37 | 38 | ||
@@ -61,12 +62,7 @@ static inline void cache_sync(void) | |||
61 | { | 62 | { |
62 | void __iomem *base = l2x0_base; | 63 | void __iomem *base = l2x0_base; |
63 | 64 | ||
64 | #ifdef CONFIG_PL310_ERRATA_753970 | 65 | writel_relaxed(0, base + sync_reg_offset); |
65 | /* write to an unmmapped register */ | ||
66 | writel_relaxed(0, base + L2X0_DUMMY_REG); | ||
67 | #else | ||
68 | writel_relaxed(0, base + L2X0_CACHE_SYNC); | ||
69 | #endif | ||
70 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 66 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
71 | } | 67 | } |
72 | 68 | ||
@@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr) | |||
85 | } | 81 | } |
86 | 82 | ||
87 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) | 83 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
84 | static inline void debug_writel(unsigned long val) | ||
85 | { | ||
86 | if (outer_cache.set_debug) | ||
87 | outer_cache.set_debug(val); | ||
88 | } | ||
88 | 89 | ||
89 | #define debug_writel(val) outer_cache.set_debug(val) | 90 | static void pl310_set_debug(unsigned long val) |
90 | |||
91 | static void l2x0_set_debug(unsigned long val) | ||
92 | { | 91 | { |
93 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); | 92 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); |
94 | } | 93 | } |
@@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val) | |||
98 | { | 97 | { |
99 | } | 98 | } |
100 | 99 | ||
101 | #define l2x0_set_debug NULL | 100 | #define pl310_set_debug NULL |
102 | #endif | 101 | #endif |
103 | 102 | ||
104 | #ifdef CONFIG_PL310_ERRATA_588369 | 103 | #ifdef CONFIG_PL310_ERRATA_588369 |
@@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
331 | else | 330 | else |
332 | ways = 8; | 331 | ways = 8; |
333 | type = "L310"; | 332 | type = "L310"; |
333 | #ifdef CONFIG_PL310_ERRATA_753970 | ||
334 | /* Unmapped register. */ | ||
335 | sync_reg_offset = L2X0_DUMMY_REG; | ||
336 | #endif | ||
337 | outer_cache.set_debug = pl310_set_debug; | ||
334 | break; | 338 | break; |
335 | case L2X0_CACHE_ID_PART_L210: | 339 | case L2X0_CACHE_ID_PART_L210: |
336 | ways = (aux >> 13) & 0xf; | 340 | ways = (aux >> 13) & 0xf; |
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
379 | outer_cache.flush_all = l2x0_flush_all; | 383 | outer_cache.flush_all = l2x0_flush_all; |
380 | outer_cache.inv_all = l2x0_inv_all; | 384 | outer_cache.inv_all = l2x0_inv_all; |
381 | outer_cache.disable = l2x0_disable; | 385 | outer_cache.disable = l2x0_disable; |
382 | outer_cache.set_debug = l2x0_set_debug; | ||
383 | 386 | ||
384 | printk(KERN_INFO "%s cache controller enabled\n", type); | 387 | printk(KERN_INFO "%s cache controller enabled\n", type); |
385 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", | 388 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |