diff options
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 34 |
1 files changed, 21 insertions, 13 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 6911b8b2745c..c2f37390308a 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
352 | /* Unmapped register. */ | 352 | /* Unmapped register. */ |
353 | sync_reg_offset = L2X0_DUMMY_REG; | 353 | sync_reg_offset = L2X0_DUMMY_REG; |
354 | #endif | 354 | #endif |
355 | outer_cache.set_debug = pl310_set_debug; | 355 | if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0) |
356 | outer_cache.set_debug = pl310_set_debug; | ||
356 | break; | 357 | break; |
357 | case L2X0_CACHE_ID_PART_L210: | 358 | case L2X0_CACHE_ID_PART_L210: |
358 | ways = (aux >> 13) & 0xf; | 359 | ways = (aux >> 13) & 0xf; |
@@ -459,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end, | |||
459 | unsigned long flags; | 460 | unsigned long flags; |
460 | 461 | ||
461 | raw_spin_lock_irqsave(&l2x0_lock, flags); | 462 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
462 | writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); | 463 | writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); |
463 | writel(end, l2x0_base + offset); | 464 | writel_relaxed(end, l2x0_base + offset); |
464 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | 465 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
465 | 466 | ||
466 | cache_sync(); | 467 | cache_sync(); |
@@ -505,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end) | |||
505 | 506 | ||
506 | static void aurora_flush_range(unsigned long start, unsigned long end) | 507 | static void aurora_flush_range(unsigned long start, unsigned long end) |
507 | { | 508 | { |
508 | if (!l2_wt_override) { | 509 | start &= ~(CACHE_LINE_SIZE - 1); |
509 | start &= ~(CACHE_LINE_SIZE - 1); | 510 | end = ALIGN(end, CACHE_LINE_SIZE); |
510 | end = ALIGN(end, CACHE_LINE_SIZE); | 511 | while (start != end) { |
511 | while (start != end) { | 512 | unsigned long range_end = calc_range_end(start, end); |
512 | unsigned long range_end = calc_range_end(start, end); | 513 | /* |
514 | * If L2 is forced to WT, the L2 will always be clean and we | ||
515 | * just need to invalidate. | ||
516 | */ | ||
517 | if (l2_wt_override) | ||
513 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | 518 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, |
514 | AURORA_FLUSH_RANGE_REG); | 519 | AURORA_INVAL_RANGE_REG); |
515 | start = range_end; | 520 | else |
516 | } | 521 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, |
522 | AURORA_FLUSH_RANGE_REG); | ||
523 | start = range_end; | ||
517 | } | 524 | } |
518 | } | 525 | } |
519 | 526 | ||
@@ -668,8 +675,9 @@ static void pl310_resume(void) | |||
668 | static void aurora_resume(void) | 675 | static void aurora_resume(void) |
669 | { | 676 | { |
670 | if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | 677 | if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { |
671 | writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL); | 678 | writel_relaxed(l2x0_saved_regs.aux_ctrl, |
672 | writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); | 679 | l2x0_base + L2X0_AUX_CTRL); |
680 | writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); | ||
673 | } | 681 | } |
674 | } | 682 | } |
675 | 683 | ||