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Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c46
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3f9b9980478e..8ac9e9f84790 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -29,7 +29,7 @@
29#define CACHE_LINE_SIZE 32 29#define CACHE_LINE_SIZE 32
30 30
31static void __iomem *l2x0_base; 31static void __iomem *l2x0_base;
32static DEFINE_SPINLOCK(l2x0_lock); 32static DEFINE_RAW_SPINLOCK(l2x0_lock);
33static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 33static uint32_t l2x0_way_mask; /* Bitmask of active ways */
34static uint32_t l2x0_size; 34static uint32_t l2x0_size;
35 35
@@ -126,9 +126,9 @@ static void l2x0_cache_sync(void)
126{ 126{
127 unsigned long flags; 127 unsigned long flags;
128 128
129 spin_lock_irqsave(&l2x0_lock, flags); 129 raw_spin_lock_irqsave(&l2x0_lock, flags);
130 cache_sync(); 130 cache_sync();
131 spin_unlock_irqrestore(&l2x0_lock, flags); 131 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
132} 132}
133 133
134static void __l2x0_flush_all(void) 134static void __l2x0_flush_all(void)
@@ -145,9 +145,9 @@ static void l2x0_flush_all(void)
145 unsigned long flags; 145 unsigned long flags;
146 146
147 /* clean all ways */ 147 /* clean all ways */
148 spin_lock_irqsave(&l2x0_lock, flags); 148 raw_spin_lock_irqsave(&l2x0_lock, flags);
149 __l2x0_flush_all(); 149 __l2x0_flush_all();
150 spin_unlock_irqrestore(&l2x0_lock, flags); 150 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
151} 151}
152 152
153static void l2x0_clean_all(void) 153static void l2x0_clean_all(void)
@@ -155,11 +155,11 @@ static void l2x0_clean_all(void)
155 unsigned long flags; 155 unsigned long flags;
156 156
157 /* clean all ways */ 157 /* clean all ways */
158 spin_lock_irqsave(&l2x0_lock, flags); 158 raw_spin_lock_irqsave(&l2x0_lock, flags);
159 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); 159 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
160 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); 160 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
161 cache_sync(); 161 cache_sync();
162 spin_unlock_irqrestore(&l2x0_lock, flags); 162 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
163} 163}
164 164
165static void l2x0_inv_all(void) 165static void l2x0_inv_all(void)
@@ -167,13 +167,13 @@ static void l2x0_inv_all(void)
167 unsigned long flags; 167 unsigned long flags;
168 168
169 /* invalidate all ways */ 169 /* invalidate all ways */
170 spin_lock_irqsave(&l2x0_lock, flags); 170 raw_spin_lock_irqsave(&l2x0_lock, flags);
171 /* Invalidating when L2 is enabled is a nono */ 171 /* Invalidating when L2 is enabled is a nono */
172 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); 172 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
173 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 173 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
174 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 174 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
175 cache_sync(); 175 cache_sync();
176 spin_unlock_irqrestore(&l2x0_lock, flags); 176 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
177} 177}
178 178
179static void l2x0_inv_range(unsigned long start, unsigned long end) 179static void l2x0_inv_range(unsigned long start, unsigned long end)
@@ -181,7 +181,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
181 void __iomem *base = l2x0_base; 181 void __iomem *base = l2x0_base;
182 unsigned long flags; 182 unsigned long flags;
183 183
184 spin_lock_irqsave(&l2x0_lock, flags); 184 raw_spin_lock_irqsave(&l2x0_lock, flags);
185 if (start & (CACHE_LINE_SIZE - 1)) { 185 if (start & (CACHE_LINE_SIZE - 1)) {
186 start &= ~(CACHE_LINE_SIZE - 1); 186 start &= ~(CACHE_LINE_SIZE - 1);
187 debug_writel(0x03); 187 debug_writel(0x03);
@@ -206,13 +206,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
206 } 206 }
207 207
208 if (blk_end < end) { 208 if (blk_end < end) {
209 spin_unlock_irqrestore(&l2x0_lock, flags); 209 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
210 spin_lock_irqsave(&l2x0_lock, flags); 210 raw_spin_lock_irqsave(&l2x0_lock, flags);
211 } 211 }
212 } 212 }
213 cache_wait(base + L2X0_INV_LINE_PA, 1); 213 cache_wait(base + L2X0_INV_LINE_PA, 1);
214 cache_sync(); 214 cache_sync();
215 spin_unlock_irqrestore(&l2x0_lock, flags); 215 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
216} 216}
217 217
218static void l2x0_clean_range(unsigned long start, unsigned long end) 218static void l2x0_clean_range(unsigned long start, unsigned long end)
@@ -225,7 +225,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
225 return; 225 return;
226 } 226 }
227 227
228 spin_lock_irqsave(&l2x0_lock, flags); 228 raw_spin_lock_irqsave(&l2x0_lock, flags);
229 start &= ~(CACHE_LINE_SIZE - 1); 229 start &= ~(CACHE_LINE_SIZE - 1);
230 while (start < end) { 230 while (start < end) {
231 unsigned long blk_end = start + min(end - start, 4096UL); 231 unsigned long blk_end = start + min(end - start, 4096UL);
@@ -236,13 +236,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
236 } 236 }
237 237
238 if (blk_end < end) { 238 if (blk_end < end) {
239 spin_unlock_irqrestore(&l2x0_lock, flags); 239 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
240 spin_lock_irqsave(&l2x0_lock, flags); 240 raw_spin_lock_irqsave(&l2x0_lock, flags);
241 } 241 }
242 } 242 }
243 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 243 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
244 cache_sync(); 244 cache_sync();
245 spin_unlock_irqrestore(&l2x0_lock, flags); 245 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
246} 246}
247 247
248static void l2x0_flush_range(unsigned long start, unsigned long end) 248static void l2x0_flush_range(unsigned long start, unsigned long end)
@@ -255,7 +255,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
255 return; 255 return;
256 } 256 }
257 257
258 spin_lock_irqsave(&l2x0_lock, flags); 258 raw_spin_lock_irqsave(&l2x0_lock, flags);
259 start &= ~(CACHE_LINE_SIZE - 1); 259 start &= ~(CACHE_LINE_SIZE - 1);
260 while (start < end) { 260 while (start < end) {
261 unsigned long blk_end = start + min(end - start, 4096UL); 261 unsigned long blk_end = start + min(end - start, 4096UL);
@@ -268,24 +268,24 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
268 debug_writel(0x00); 268 debug_writel(0x00);
269 269
270 if (blk_end < end) { 270 if (blk_end < end) {
271 spin_unlock_irqrestore(&l2x0_lock, flags); 271 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
272 spin_lock_irqsave(&l2x0_lock, flags); 272 raw_spin_lock_irqsave(&l2x0_lock, flags);
273 } 273 }
274 } 274 }
275 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 275 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
276 cache_sync(); 276 cache_sync();
277 spin_unlock_irqrestore(&l2x0_lock, flags); 277 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
278} 278}
279 279
280static void l2x0_disable(void) 280static void l2x0_disable(void)
281{ 281{
282 unsigned long flags; 282 unsigned long flags;
283 283
284 spin_lock_irqsave(&l2x0_lock, flags); 284 raw_spin_lock_irqsave(&l2x0_lock, flags);
285 __l2x0_flush_all(); 285 __l2x0_flush_all();
286 writel_relaxed(0, l2x0_base + L2X0_CTRL); 286 writel_relaxed(0, l2x0_base + L2X0_CTRL);
287 dsb(); 287 dsb();
288 spin_unlock_irqrestore(&l2x0_lock, flags); 288 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
289} 289}
290 290
291static void l2x0_unlock(__u32 cache_id) 291static void l2x0_unlock(__u32 cache_id)