diff options
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 72 |
1 files changed, 62 insertions, 10 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index cb8fc6573b1b..07334632d3e2 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -42,6 +42,57 @@ static inline void cache_sync(void) | |||
42 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 42 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
43 | } | 43 | } |
44 | 44 | ||
45 | static inline void l2x0_clean_line(unsigned long addr) | ||
46 | { | ||
47 | void __iomem *base = l2x0_base; | ||
48 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
49 | writel(addr, base + L2X0_CLEAN_LINE_PA); | ||
50 | } | ||
51 | |||
52 | static inline void l2x0_inv_line(unsigned long addr) | ||
53 | { | ||
54 | void __iomem *base = l2x0_base; | ||
55 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
56 | writel(addr, base + L2X0_INV_LINE_PA); | ||
57 | } | ||
58 | |||
59 | #ifdef CONFIG_PL310_ERRATA_588369 | ||
60 | static void debug_writel(unsigned long val) | ||
61 | { | ||
62 | extern void omap_smc1(u32 fn, u32 arg); | ||
63 | |||
64 | /* | ||
65 | * Texas Instrument secure monitor api to modify the | ||
66 | * PL310 Debug Control Register. | ||
67 | */ | ||
68 | omap_smc1(0x100, val); | ||
69 | } | ||
70 | |||
71 | static inline void l2x0_flush_line(unsigned long addr) | ||
72 | { | ||
73 | void __iomem *base = l2x0_base; | ||
74 | |||
75 | /* Clean by PA followed by Invalidate by PA */ | ||
76 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
77 | writel(addr, base + L2X0_CLEAN_LINE_PA); | ||
78 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
79 | writel(addr, base + L2X0_INV_LINE_PA); | ||
80 | } | ||
81 | #else | ||
82 | |||
83 | /* Optimised out for non-errata case */ | ||
84 | static inline void debug_writel(unsigned long val) | ||
85 | { | ||
86 | } | ||
87 | |||
88 | static inline void l2x0_flush_line(unsigned long addr) | ||
89 | { | ||
90 | void __iomem *base = l2x0_base; | ||
91 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | ||
92 | writel(addr, base + L2X0_CLEAN_INV_LINE_PA); | ||
93 | } | ||
94 | #endif | ||
95 | |||
45 | static inline void l2x0_inv_all(void) | 96 | static inline void l2x0_inv_all(void) |
46 | { | 97 | { |
47 | unsigned long flags; | 98 | unsigned long flags; |
@@ -62,23 +113,24 @@ static void l2x0_inv_range(unsigned long start, unsigned long end) | |||
62 | spin_lock_irqsave(&l2x0_lock, flags); | 113 | spin_lock_irqsave(&l2x0_lock, flags); |
63 | if (start & (CACHE_LINE_SIZE - 1)) { | 114 | if (start & (CACHE_LINE_SIZE - 1)) { |
64 | start &= ~(CACHE_LINE_SIZE - 1); | 115 | start &= ~(CACHE_LINE_SIZE - 1); |
65 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 116 | debug_writel(0x03); |
66 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | 117 | l2x0_flush_line(start); |
118 | debug_writel(0x00); | ||
67 | start += CACHE_LINE_SIZE; | 119 | start += CACHE_LINE_SIZE; |
68 | } | 120 | } |
69 | 121 | ||
70 | if (end & (CACHE_LINE_SIZE - 1)) { | 122 | if (end & (CACHE_LINE_SIZE - 1)) { |
71 | end &= ~(CACHE_LINE_SIZE - 1); | 123 | end &= ~(CACHE_LINE_SIZE - 1); |
72 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 124 | debug_writel(0x03); |
73 | writel(end, base + L2X0_CLEAN_INV_LINE_PA); | 125 | l2x0_flush_line(end); |
126 | debug_writel(0x00); | ||
74 | } | 127 | } |
75 | 128 | ||
76 | while (start < end) { | 129 | while (start < end) { |
77 | unsigned long blk_end = start + min(end - start, 4096UL); | 130 | unsigned long blk_end = start + min(end - start, 4096UL); |
78 | 131 | ||
79 | while (start < blk_end) { | 132 | while (start < blk_end) { |
80 | cache_wait(base + L2X0_INV_LINE_PA, 1); | 133 | l2x0_inv_line(start); |
81 | writel(start, base + L2X0_INV_LINE_PA); | ||
82 | start += CACHE_LINE_SIZE; | 134 | start += CACHE_LINE_SIZE; |
83 | } | 135 | } |
84 | 136 | ||
@@ -103,8 +155,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) | |||
103 | unsigned long blk_end = start + min(end - start, 4096UL); | 155 | unsigned long blk_end = start + min(end - start, 4096UL); |
104 | 156 | ||
105 | while (start < blk_end) { | 157 | while (start < blk_end) { |
106 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | 158 | l2x0_clean_line(start); |
107 | writel(start, base + L2X0_CLEAN_LINE_PA); | ||
108 | start += CACHE_LINE_SIZE; | 159 | start += CACHE_LINE_SIZE; |
109 | } | 160 | } |
110 | 161 | ||
@@ -128,11 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) | |||
128 | while (start < end) { | 179 | while (start < end) { |
129 | unsigned long blk_end = start + min(end - start, 4096UL); | 180 | unsigned long blk_end = start + min(end - start, 4096UL); |
130 | 181 | ||
182 | debug_writel(0x03); | ||
131 | while (start < blk_end) { | 183 | while (start < blk_end) { |
132 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 184 | l2x0_flush_line(start); |
133 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | ||
134 | start += CACHE_LINE_SIZE; | 185 | start += CACHE_LINE_SIZE; |
135 | } | 186 | } |
187 | debug_writel(0x00); | ||
136 | 188 | ||
137 | if (blk_end < end) { | 189 | if (blk_end < end) { |
138 | spin_unlock_irqrestore(&l2x0_lock, flags); | 190 | spin_unlock_irqrestore(&l2x0_lock, flags); |