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-rw-r--r--arch/arm/mm/cache-fa.S19
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index e505befe51b5..2f0c58836ae7 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -15,6 +15,7 @@
15 */ 15 */
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <asm/assembler.h>
18#include <asm/memory.h> 19#include <asm/memory.h>
19#include <asm/page.h> 20#include <asm/page.h>
20 21
@@ -45,7 +46,7 @@
45ENTRY(fa_flush_icache_all) 46ENTRY(fa_flush_icache_all)
46 mov r0, #0 47 mov r0, #0
47 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
48 mov pc, lr 49 ret lr
49ENDPROC(fa_flush_icache_all) 50ENDPROC(fa_flush_icache_all)
50 51
51/* 52/*
@@ -71,7 +72,7 @@ __flush_whole_cache:
71 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
72 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 73 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
73 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 74 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
74 mov pc, lr 75 ret lr
75 76
76/* 77/*
77 * flush_user_cache_range(start, end, flags) 78 * flush_user_cache_range(start, end, flags)
@@ -99,7 +100,7 @@ ENTRY(fa_flush_user_cache_range)
99 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
100 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 101 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
101 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 102 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
102 mov pc, lr 103 ret lr
103 104
104/* 105/*
105 * coherent_kern_range(start, end) 106 * coherent_kern_range(start, end)
@@ -135,7 +136,7 @@ ENTRY(fa_coherent_user_range)
135 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
136 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 137 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
137 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
138 mov pc, lr 139 ret lr
139 140
140/* 141/*
141 * flush_kern_dcache_area(void *addr, size_t size) 142 * flush_kern_dcache_area(void *addr, size_t size)
@@ -155,7 +156,7 @@ ENTRY(fa_flush_kern_dcache_area)
155 mov r0, #0 156 mov r0, #0
156 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
157 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 158 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
158 mov pc, lr 159 ret lr
159 160
160/* 161/*
161 * dma_inv_range(start, end) 162 * dma_inv_range(start, end)
@@ -181,7 +182,7 @@ fa_dma_inv_range:
181 blo 1b 182 blo 1b
182 mov r0, #0 183 mov r0, #0
183 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 184 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
184 mov pc, lr 185 ret lr
185 186
186/* 187/*
187 * dma_clean_range(start, end) 188 * dma_clean_range(start, end)
@@ -199,7 +200,7 @@ fa_dma_clean_range:
199 blo 1b 200 blo 1b
200 mov r0, #0 201 mov r0, #0
201 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
202 mov pc, lr 203 ret lr
203 204
204/* 205/*
205 * dma_flush_range(start,end) 206 * dma_flush_range(start,end)
@@ -214,7 +215,7 @@ ENTRY(fa_dma_flush_range)
214 blo 1b 215 blo 1b
215 mov r0, #0 216 mov r0, #0
216 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 217 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
217 mov pc, lr 218 ret lr
218 219
219/* 220/*
220 * dma_map_area(start, size, dir) 221 * dma_map_area(start, size, dir)
@@ -237,7 +238,7 @@ ENDPROC(fa_dma_map_area)
237 * - dir - DMA direction 238 * - dir - DMA direction
238 */ 239 */
239ENTRY(fa_dma_unmap_area) 240ENTRY(fa_dma_unmap_area)
240 mov pc, lr 241 ret lr
241ENDPROC(fa_dma_unmap_area) 242ENDPROC(fa_dma_unmap_area)
242 243
243 .globl fa_flush_kern_cache_louis 244 .globl fa_flush_kern_cache_louis