1 files changed, 16 insertions, 18 deletions
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index d7cb1bfa51a4..52162d59407a 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -9,34 +9,32 @@
 *
 */
-        .macro  do_thumb_abort
+        .macro  do_thumb_abort, fsr, pc, psr, tmp
-        tst     r3, #PSR_T_BIT
+        tst     \psr, #PSR_T_BIT
        beq     not_thumb
-        ldrh    r3, [r2]                        @ Read aborted Thumb instruction
+        ldrh    \tmp, [\pc]                     @ Read aborted Thumb instruction
-        and     r3, r3, # 0xfe00                @ Mask opcode field
+        and     \tmp, \tmp, # 0xfe00            @ Mask opcode field
-        cmp     r3, # 0x5600                    @ Is it ldrsb?
+        cmp     \tmp, # 0x5600                  @ Is it ldrsb?
-        orreq   r3, r3, #1 << 11                @ Set L-bit if yes
+        orreq   \tmp, \tmp, #1 << 11            @ Set L-bit if yes
-        tst     r3, #1 << 11                    @ L = 0 -> write
+        tst     \tmp, #1 << 11                  @ L = 0 -> write
-        orreq   r1, r1, #1 << 11                @ yes.
+        orreq   \psr, \psr, #1 << 11            @ yes.
-        mov     pc, lr
+        b       do_DataAbort
 not_thumb:
        .endm
 /*
- * We check for the following insturction encoding for LDRD.
+ * We check for the following instruction encoding for LDRD.
 *
- * [27:25] == 0
+ * [27:25] == 000
 *   [7:4] == 1101
 *    [20] == 0
 */
-        .macro  do_ldrd_abort
+        .macro  do_ldrd_abort, tmp, insn
-        tst     r3, #0x0e000000                 @ [27:25] == 0
+        tst     \insn, #0x0e100000              @ [27:25,20] == 0
        bne     not_ldrd
-        and     r2, r3, #0x000000f0             @ [7:4] == 1101
+        and     \tmp, \insn, #0x000000f0        @ [7:4] == 1101
-        cmp     r2, #0x000000d0
+        cmp     \tmp, #0x000000d0
-        bne     not_ldrd
+        beq     do_DataAbort
-        tst     r3, #1 << 20                    @ [20] == 0
-        moveq   pc, lr
 not_ldrd:
        .endm

diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S index d7cb1bfa51a4..52162d59407a 100644 --- a/arch/arm/mm/abort-macro.S +++ b/arch/arm/mm/abort-macro.S
@@ -9,34 +9,32 @@
9	*	9	*
10	*/	10	*/
11		11
12	.macro do_thumb_abort	12	.macro do_thumb_abort, fsr, pc, psr, tmp
13	tst r3, #PSR_T_BIT	13	tst \psr, #PSR_T_BIT
14	beq not_thumb	14	beq not_thumb
15	ldrh r3, [r2] @ Read aborted Thumb instruction	15	ldrh \tmp, [\pc] @ Read aborted Thumb instruction
16	and r3, r3, # 0xfe00 @ Mask opcode field	16	and \tmp, \tmp, # 0xfe00 @ Mask opcode field
17	cmp r3, # 0x5600 @ Is it ldrsb?	17	cmp \tmp, # 0x5600 @ Is it ldrsb?
18	orreq r3, r3, #1 << 11 @ Set L-bit if yes	18	orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19	tst r3, #1 << 11 @ L = 0 -> write	19	tst \tmp, #1 << 11 @ L = 0 -> write
20	orreq r1, r1, #1 << 11 @ yes.	20	orreq \psr, \psr, #1 << 11 @ yes.
21	mov pc, lr	21	b do_DataAbort
22	not_thumb:	22	not_thumb:
23	.endm	23	.endm
24		24
25	/*	25	/*
26	* We check for the following insturction encoding for LDRD.	26	* We check for the following instruction encoding for LDRD.
27	*	27	*
28	* [27:25] == 0	28	* [27:25] == 000
29	* [7:4] == 1101	29	* [7:4] == 1101
30	* [20] == 0	30	* [20] == 0
31	*/	31	*/
32	.macro do_ldrd_abort	32	.macro do_ldrd_abort, tmp, insn
33	tst r3, #0x0e000000 @ [27:25] == 0	33	tst \insn, #0x0e100000 @ [27:25,20] == 0
34	bne not_ldrd	34	bne not_ldrd
35	and r2, r3, #0x000000f0 @ [7:4] == 1101	35	and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
36	cmp r2, #0x000000d0	36	cmp \tmp, #0x000000d0
37	bne not_ldrd	37	beq do_DataAbort
38	tst r3, #1 << 20 @ [20] == 0
39	moveq pc, lr
40	not_ldrd:	38	not_ldrd:
41	.endm	39	.endm
42		40