diff options
Diffstat (limited to 'arch/arm/mm/abort-ev6.S')
| -rw-r--r-- | arch/arm/mm/abort-ev6.S | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ff1f7cc11f87..80741992a9fc 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S | |||
| @@ -26,18 +26,23 @@ ENTRY(v6_early_abort) | |||
| 26 | mrc p15, 0, r1, c5, c0, 0 @ get FSR | 26 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
| 27 | mrc p15, 0, r0, c6, c0, 0 @ get FAR | 27 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
| 28 | /* | 28 | /* |
| 29 | * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). | 29 | * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. |
| 30 | * The test below covers all the write situations, including Java bytecodes | ||
| 31 | */ | 30 | */ |
| 32 | bic r1, r1, #1 << 11 @ clear bit 11 of FSR | 31 | #ifdef CONFIG_ARM_ERRATA_326103 |
| 32 | ldr ip, =0x4107b36 | ||
| 33 | mrc p15, 0, r3, c0, c0, 0 @ get processor id | ||
| 34 | teq ip, r3, lsr #4 @ r0 ARM1136? | ||
| 35 | bne do_DataAbort | ||
| 33 | tst r5, #PSR_J_BIT @ Java? | 36 | tst r5, #PSR_J_BIT @ Java? |
| 37 | tsteq r5, #PSR_T_BIT @ Thumb? | ||
| 34 | bne do_DataAbort | 38 | bne do_DataAbort |
| 35 | do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 | 39 | bic r1, r1, #1 << 11 @ clear bit 11 of FSR |
| 36 | ldreq r3, [r4] @ read aborted ARM instruction | 40 | ldr r3, [r4] @ read aborted ARM instruction |
| 37 | #ifdef CONFIG_CPU_ENDIAN_BE8 | 41 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 38 | reveq r3, r3 | 42 | rev r3, r3 |
| 39 | #endif | 43 | #endif |
| 40 | do_ldrd_abort tmp=ip, insn=r3 | 44 | do_ldrd_abort tmp=ip, insn=r3 |
| 41 | tst r3, #1 << 20 @ L = 0 -> write | 45 | tst r3, #1 << 20 @ L = 0 -> write |
| 42 | orreq r1, r1, #1 << 11 @ yes. | 46 | orreq r1, r1, #1 << 11 @ yes. |
| 47 | #endif | ||
| 43 | b do_DataAbort | 48 | b do_DataAbort |