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-rw-r--r--arch/arm/mm/Kconfig57
1 files changed, 30 insertions, 27 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 8d43e58f9244..e993140edd88 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -17,7 +17,7 @@ config CPU_ARM610
17 select CPU_CP15_MMU 17 select CPU_CP15_MMU
18 select CPU_COPY_V3 if MMU 18 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU 19 select CPU_TLB_V3 if MMU
20 select CPU_PABRT_NOIFAR 20 select CPU_PABRT_LEGACY
21 help 21 help
22 The ARM610 is the successor to the ARM3 processor 22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc. 23 and was produced by VLSI Technology Inc.
@@ -31,7 +31,7 @@ config CPU_ARM7TDMI
31 depends on !MMU 31 depends on !MMU
32 select CPU_32v4T 32 select CPU_32v4T
33 select CPU_ABRT_LV4T 33 select CPU_ABRT_LV4T
34 select CPU_PABRT_NOIFAR 34 select CPU_PABRT_LEGACY
35 select CPU_CACHE_V4 35 select CPU_CACHE_V4
36 help 36 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core 37 A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -49,7 +49,7 @@ config CPU_ARM710
49 select CPU_CP15_MMU 49 select CPU_CP15_MMU
50 select CPU_COPY_V3 if MMU 50 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU 51 select CPU_TLB_V3 if MMU
52 select CPU_PABRT_NOIFAR 52 select CPU_PABRT_LEGACY
53 help 53 help
54 A 32-bit RISC microprocessor based on the ARM7 processor core 54 A 32-bit RISC microprocessor based on the ARM7 processor core
55 designed by Advanced RISC Machines Ltd. The ARM710 is the 55 designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,7 +64,7 @@ config CPU_ARM720T
64 bool "Support ARM720T processor" if ARCH_INTEGRATOR 64 bool "Support ARM720T processor" if ARCH_INTEGRATOR
65 select CPU_32v4T 65 select CPU_32v4T
66 select CPU_ABRT_LV4T 66 select CPU_ABRT_LV4T
67 select CPU_PABRT_NOIFAR 67 select CPU_PABRT_LEGACY
68 select CPU_CACHE_V4 68 select CPU_CACHE_V4
69 select CPU_CACHE_VIVT 69 select CPU_CACHE_VIVT
70 select CPU_CP15_MMU 70 select CPU_CP15_MMU
@@ -83,7 +83,7 @@ config CPU_ARM740T
83 depends on !MMU 83 depends on !MMU
84 select CPU_32v4T 84 select CPU_32v4T
85 select CPU_ABRT_LV4T 85 select CPU_ABRT_LV4T
86 select CPU_PABRT_NOIFAR 86 select CPU_PABRT_LEGACY
87 select CPU_CACHE_V3 # although the core is v4t 87 select CPU_CACHE_V3 # although the core is v4t
88 select CPU_CP15_MPU 88 select CPU_CP15_MPU
89 help 89 help
@@ -100,7 +100,7 @@ config CPU_ARM9TDMI
100 depends on !MMU 100 depends on !MMU
101 select CPU_32v4T 101 select CPU_32v4T
102 select CPU_ABRT_NOMMU 102 select CPU_ABRT_NOMMU
103 select CPU_PABRT_NOIFAR 103 select CPU_PABRT_LEGACY
104 select CPU_CACHE_V4 104 select CPU_CACHE_V4
105 help 105 help
106 A 32-bit RISC microprocessor based on the ARM9 processor core 106 A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -114,7 +114,7 @@ config CPU_ARM920T
114 bool "Support ARM920T processor" if ARCH_INTEGRATOR 114 bool "Support ARM920T processor" if ARCH_INTEGRATOR
115 select CPU_32v4T 115 select CPU_32v4T
116 select CPU_ABRT_EV4T 116 select CPU_ABRT_EV4T
117 select CPU_PABRT_NOIFAR 117 select CPU_PABRT_LEGACY
118 select CPU_CACHE_V4WT 118 select CPU_CACHE_V4WT
119 select CPU_CACHE_VIVT 119 select CPU_CACHE_VIVT
120 select CPU_CP15_MMU 120 select CPU_CP15_MMU
@@ -135,7 +135,7 @@ config CPU_ARM922T
135 bool "Support ARM922T processor" if ARCH_INTEGRATOR 135 bool "Support ARM922T processor" if ARCH_INTEGRATOR
136 select CPU_32v4T 136 select CPU_32v4T
137 select CPU_ABRT_EV4T 137 select CPU_ABRT_EV4T
138 select CPU_PABRT_NOIFAR 138 select CPU_PABRT_LEGACY
139 select CPU_CACHE_V4WT 139 select CPU_CACHE_V4WT
140 select CPU_CACHE_VIVT 140 select CPU_CACHE_VIVT
141 select CPU_CP15_MMU 141 select CPU_CP15_MMU
@@ -154,7 +154,7 @@ config CPU_ARM925T
154 bool "Support ARM925T processor" if ARCH_OMAP1 154 bool "Support ARM925T processor" if ARCH_OMAP1
155 select CPU_32v4T 155 select CPU_32v4T
156 select CPU_ABRT_EV4T 156 select CPU_ABRT_EV4T
157 select CPU_PABRT_NOIFAR 157 select CPU_PABRT_LEGACY
158 select CPU_CACHE_V4WT 158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT 159 select CPU_CACHE_VIVT
160 select CPU_CP15_MMU 160 select CPU_CP15_MMU
@@ -173,7 +173,7 @@ config CPU_ARM926T
173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
174 select CPU_32v5 174 select CPU_32v5
175 select CPU_ABRT_EV5TJ 175 select CPU_ABRT_EV5TJ
176 select CPU_PABRT_NOIFAR 176 select CPU_PABRT_LEGACY
177 select CPU_CACHE_VIVT 177 select CPU_CACHE_VIVT
178 select CPU_CP15_MMU 178 select CPU_CP15_MMU
179 select CPU_COPY_V4WB if MMU 179 select CPU_COPY_V4WB if MMU
@@ -191,7 +191,7 @@ config CPU_FA526
191 bool 191 bool
192 select CPU_32v4 192 select CPU_32v4
193 select CPU_ABRT_EV4 193 select CPU_ABRT_EV4
194 select CPU_PABRT_NOIFAR 194 select CPU_PABRT_LEGACY
195 select CPU_CACHE_VIVT 195 select CPU_CACHE_VIVT
196 select CPU_CP15_MMU 196 select CPU_CP15_MMU
197 select CPU_CACHE_FA 197 select CPU_CACHE_FA
@@ -210,7 +210,7 @@ config CPU_ARM940T
210 depends on !MMU 210 depends on !MMU
211 select CPU_32v4T 211 select CPU_32v4T
212 select CPU_ABRT_NOMMU 212 select CPU_ABRT_NOMMU
213 select CPU_PABRT_NOIFAR 213 select CPU_PABRT_LEGACY
214 select CPU_CACHE_VIVT 214 select CPU_CACHE_VIVT
215 select CPU_CP15_MPU 215 select CPU_CP15_MPU
216 help 216 help
@@ -228,7 +228,7 @@ config CPU_ARM946E
228 depends on !MMU 228 depends on !MMU
229 select CPU_32v5 229 select CPU_32v5
230 select CPU_ABRT_NOMMU 230 select CPU_ABRT_NOMMU
231 select CPU_PABRT_NOIFAR 231 select CPU_PABRT_LEGACY
232 select CPU_CACHE_VIVT 232 select CPU_CACHE_VIVT
233 select CPU_CP15_MPU 233 select CPU_CP15_MPU
234 help 234 help
@@ -244,7 +244,7 @@ config CPU_ARM1020
244 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 244 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
245 select CPU_32v5 245 select CPU_32v5
246 select CPU_ABRT_EV4T 246 select CPU_ABRT_EV4T
247 select CPU_PABRT_NOIFAR 247 select CPU_PABRT_LEGACY
248 select CPU_CACHE_V4WT 248 select CPU_CACHE_V4WT
249 select CPU_CACHE_VIVT 249 select CPU_CACHE_VIVT
250 select CPU_CP15_MMU 250 select CPU_CP15_MMU
@@ -262,7 +262,7 @@ config CPU_ARM1020E
262 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 262 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
263 select CPU_32v5 263 select CPU_32v5
264 select CPU_ABRT_EV4T 264 select CPU_ABRT_EV4T
265 select CPU_PABRT_NOIFAR 265 select CPU_PABRT_LEGACY
266 select CPU_CACHE_V4WT 266 select CPU_CACHE_V4WT
267 select CPU_CACHE_VIVT 267 select CPU_CACHE_VIVT
268 select CPU_CP15_MMU 268 select CPU_CP15_MMU
@@ -275,7 +275,7 @@ config CPU_ARM1022
275 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 275 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
276 select CPU_32v5 276 select CPU_32v5
277 select CPU_ABRT_EV4T 277 select CPU_ABRT_EV4T
278 select CPU_PABRT_NOIFAR 278 select CPU_PABRT_LEGACY
279 select CPU_CACHE_VIVT 279 select CPU_CACHE_VIVT
280 select CPU_CP15_MMU 280 select CPU_CP15_MMU
281 select CPU_COPY_V4WB if MMU # can probably do better 281 select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,7 +293,7 @@ config CPU_ARM1026
293 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 293 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
294 select CPU_32v5 294 select CPU_32v5
295 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 295 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
296 select CPU_PABRT_NOIFAR 296 select CPU_PABRT_LEGACY
297 select CPU_CACHE_VIVT 297 select CPU_CACHE_VIVT
298 select CPU_CP15_MMU 298 select CPU_CP15_MMU
299 select CPU_COPY_V4WB if MMU # can probably do better 299 select CPU_COPY_V4WB if MMU # can probably do better
@@ -311,7 +311,7 @@ config CPU_SA110
311 select CPU_32v3 if ARCH_RPC 311 select CPU_32v3 if ARCH_RPC
312 select CPU_32v4 if !ARCH_RPC 312 select CPU_32v4 if !ARCH_RPC
313 select CPU_ABRT_EV4 313 select CPU_ABRT_EV4
314 select CPU_PABRT_NOIFAR 314 select CPU_PABRT_LEGACY
315 select CPU_CACHE_V4WB 315 select CPU_CACHE_V4WB
316 select CPU_CACHE_VIVT 316 select CPU_CACHE_VIVT
317 select CPU_CP15_MMU 317 select CPU_CP15_MMU
@@ -331,7 +331,7 @@ config CPU_SA1100
331 bool 331 bool
332 select CPU_32v4 332 select CPU_32v4
333 select CPU_ABRT_EV4 333 select CPU_ABRT_EV4
334 select CPU_PABRT_NOIFAR 334 select CPU_PABRT_LEGACY
335 select CPU_CACHE_V4WB 335 select CPU_CACHE_V4WB
336 select CPU_CACHE_VIVT 336 select CPU_CACHE_VIVT
337 select CPU_CP15_MMU 337 select CPU_CP15_MMU
@@ -342,7 +342,7 @@ config CPU_XSCALE
342 bool 342 bool
343 select CPU_32v5 343 select CPU_32v5
344 select CPU_ABRT_EV5T 344 select CPU_ABRT_EV5T
345 select CPU_PABRT_NOIFAR 345 select CPU_PABRT_LEGACY
346 select CPU_CACHE_VIVT 346 select CPU_CACHE_VIVT
347 select CPU_CP15_MMU 347 select CPU_CP15_MMU
348 select CPU_TLB_V4WBI if MMU 348 select CPU_TLB_V4WBI if MMU
@@ -352,7 +352,7 @@ config CPU_XSC3
352 bool 352 bool
353 select CPU_32v5 353 select CPU_32v5
354 select CPU_ABRT_EV5T 354 select CPU_ABRT_EV5T
355 select CPU_PABRT_NOIFAR 355 select CPU_PABRT_LEGACY
356 select CPU_CACHE_VIVT 356 select CPU_CACHE_VIVT
357 select CPU_CP15_MMU 357 select CPU_CP15_MMU
358 select CPU_TLB_V4WBI if MMU 358 select CPU_TLB_V4WBI if MMU
@@ -363,7 +363,7 @@ config CPU_MOHAWK
363 bool 363 bool
364 select CPU_32v5 364 select CPU_32v5
365 select CPU_ABRT_EV5T 365 select CPU_ABRT_EV5T
366 select CPU_PABRT_NOIFAR 366 select CPU_PABRT_LEGACY
367 select CPU_CACHE_VIVT 367 select CPU_CACHE_VIVT
368 select CPU_CP15_MMU 368 select CPU_CP15_MMU
369 select CPU_TLB_V4WBI if MMU 369 select CPU_TLB_V4WBI if MMU
@@ -374,7 +374,7 @@ config CPU_FEROCEON
374 bool 374 bool
375 select CPU_32v5 375 select CPU_32v5
376 select CPU_ABRT_EV5T 376 select CPU_ABRT_EV5T
377 select CPU_PABRT_NOIFAR 377 select CPU_PABRT_LEGACY
378 select CPU_CACHE_VIVT 378 select CPU_CACHE_VIVT
379 select CPU_CP15_MMU 379 select CPU_CP15_MMU
380 select CPU_COPY_FEROCEON if MMU 380 select CPU_COPY_FEROCEON if MMU
@@ -394,7 +394,7 @@ config CPU_V6
394 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 394 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
395 select CPU_32v6 395 select CPU_32v6
396 select CPU_ABRT_EV6 396 select CPU_ABRT_EV6
397 select CPU_PABRT_NOIFAR 397 select CPU_PABRT_V6
398 select CPU_CACHE_V6 398 select CPU_CACHE_V6
399 select CPU_CACHE_VIPT 399 select CPU_CACHE_VIPT
400 select CPU_CP15_MMU 400 select CPU_CP15_MMU
@@ -420,7 +420,7 @@ config CPU_V7
420 select CPU_32v6K 420 select CPU_32v6K
421 select CPU_32v7 421 select CPU_32v7
422 select CPU_ABRT_EV7 422 select CPU_ABRT_EV7
423 select CPU_PABRT_IFAR 423 select CPU_PABRT_V7
424 select CPU_CACHE_V7 424 select CPU_CACHE_V7
425 select CPU_CACHE_VIPT 425 select CPU_CACHE_VIPT
426 select CPU_CP15_MMU 426 select CPU_CP15_MMU
@@ -482,10 +482,13 @@ config CPU_ABRT_EV6
482config CPU_ABRT_EV7 482config CPU_ABRT_EV7
483 bool 483 bool
484 484
485config CPU_PABRT_IFAR 485config CPU_PABRT_LEGACY
486 bool 486 bool
487 487
488config CPU_PABRT_NOIFAR 488config CPU_PABRT_V6
489 bool
490
491config CPU_PABRT_V7
489 bool 492 bool
490 493
491# The cache model 494# The cache model
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 02:23:07 -0500