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-rw-r--r--arch/arm/mach-w90x900/cpu.c1
-rw-r--r--arch/arm/mach-w90x900/dev.c2
-rw-r--r--arch/arm/mach-w90x900/include/mach/system.h15
-rw-r--r--arch/arm/mach-w90x900/include/mach/uncompress.h10
-rw-r--r--arch/arm/mach-w90x900/time.c64
5 files changed, 63 insertions, 29 deletions
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 921cef991bf0..20dc0c96214d 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -96,6 +96,7 @@ static struct clk_lookup nuc900_clkregs[] = {
96 96
97struct plat_serial8250_port nuc900_uart_data[] = { 97struct plat_serial8250_port nuc900_uart_data[] = {
98 NUC900_8250PORT(UART0), 98 NUC900_8250PORT(UART0),
99 {},
99}; 100};
100 101
101struct platform_device nuc900_serial_device = { 102struct platform_device nuc900_serial_device = {
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 51f17b753348..ec711f4b4019 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -197,7 +197,7 @@ static struct platform_device nuc900_device_emc = {
197 197
198/* SPI device */ 198/* SPI device */
199 199
200static struct w90p910_spi_info nuc900_spiflash_data = { 200static struct nuc900_spi_info nuc900_spiflash_data = {
201 .num_cs = 1, 201 .num_cs = 1,
202 .lsb = 0, 202 .lsb = 0,
203 .txneg = 1, 203 .txneg = 1,
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
index 940640066857..ce228bdc66dd 100644
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ b/arch/arm/mach-w90x900/include/mach/system.h
@@ -15,7 +15,15 @@
15 * 15 *
16 */ 16 */
17 17
18#include <linux/io.h>
18#include <asm/proc-fns.h> 19#include <asm/proc-fns.h>
20#include <mach/map.h>
21#include <mach/regs-timer.h>
22
23#define WTCR (TMR_BA + 0x1C)
24#define WTCLK (1 << 10)
25#define WTE (1 << 7)
26#define WTRE (1 << 1)
19 27
20static void arch_idle(void) 28static void arch_idle(void)
21{ 29{
@@ -23,6 +31,11 @@ static void arch_idle(void)
23 31
24static void arch_reset(char mode, const char *cmd) 32static void arch_reset(char mode, const char *cmd)
25{ 33{
26 cpu_reset(0); 34 if (mode == 's') {
35 /* Jump into ROM at address 0 */
36 cpu_reset(0);
37 } else {
38 __raw_writel(WTE | WTRE | WTCLK, WTCR);
39 }
27} 40}
28 41
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 050d9fe5ae1b..56f1a74d7016 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -22,11 +22,21 @@
22 22
23#include <mach/regs-serial.h> 23#include <mach/regs-serial.h>
24#include <mach/map.h> 24#include <mach/map.h>
25#include <linux/serial_reg.h>
25 26
26#define arch_decomp_wdog() 27#define arch_decomp_wdog()
27 28
29#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
30static volatile u32 * uart_base = (u32 *)UART0_PA;
31
28static void putc(int ch) 32static void putc(int ch)
29{ 33{
34 /* Check THRE and TEMT bits before we transmit the character.
35 */
36 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
37 barrier();
38
39 *uart_base = ch;
30} 40}
31 41
32static inline void flush(void) 42static inline void flush(void)
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 4128af870b41..b80f769bc135 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -42,7 +42,10 @@
42#define TICKS_PER_SEC 100 42#define TICKS_PER_SEC 100
43#define PRESCALE 0x63 /* Divider = prescale + 1 */ 43#define PRESCALE 0x63 /* Divider = prescale + 1 */
44 44
45unsigned int timer0_load; 45#define TDR_SHIFT 24
46#define TDR_MASK ((1 << TDR_SHIFT) - 1)
47
48static unsigned int timer0_load;
46 49
47static void nuc900_clockevent_setmode(enum clock_event_mode mode, 50static void nuc900_clockevent_setmode(enum clock_event_mode mode,
48 struct clock_event_device *clk) 51 struct clock_event_device *clk)
@@ -88,7 +91,7 @@ static int nuc900_clockevent_setnextevent(unsigned long evt,
88static struct clock_event_device nuc900_clockevent_device = { 91static struct clock_event_device nuc900_clockevent_device = {
89 .name = "nuc900-timer0", 92 .name = "nuc900-timer0",
90 .shift = 32, 93 .shift = 32,
91 .features = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
92 .set_mode = nuc900_clockevent_setmode, 95 .set_mode = nuc900_clockevent_setmode,
93 .set_next_event = nuc900_clockevent_setnextevent, 96 .set_next_event = nuc900_clockevent_setnextevent,
94 .rating = 300, 97 .rating = 300,
@@ -112,8 +115,23 @@ static struct irqaction nuc900_timer0_irq = {
112 .handler = nuc900_timer0_interrupt, 115 .handler = nuc900_timer0_interrupt,
113}; 116};
114 117
115static void __init nuc900_clockevents_init(unsigned int rate) 118static void __init nuc900_clockevents_init(void)
116{ 119{
120 unsigned int rate;
121 struct clk *clk = clk_get(NULL, "timer0");
122
123 BUG_ON(IS_ERR(clk));
124
125 __raw_writel(0x00, REG_TCSR0);
126
127 clk_enable(clk);
128 rate = clk_get_rate(clk) / (PRESCALE + 1);
129
130 timer0_load = (rate / TICKS_PER_SEC);
131
132 __raw_writel(RESETINT, REG_TISR);
133 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
134
117 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC, 135 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
118 nuc900_clockevent_device.shift); 136 nuc900_clockevent_device.shift);
119 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff, 137 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
@@ -127,26 +145,35 @@ static void __init nuc900_clockevents_init(unsigned int rate)
127 145
128static cycle_t nuc900_get_cycles(struct clocksource *cs) 146static cycle_t nuc900_get_cycles(struct clocksource *cs)
129{ 147{
130 return ~__raw_readl(REG_TDR1); 148 return (~__raw_readl(REG_TDR1)) & TDR_MASK;
131} 149}
132 150
133static struct clocksource clocksource_nuc900 = { 151static struct clocksource clocksource_nuc900 = {
134 .name = "nuc900-timer1", 152 .name = "nuc900-timer1",
135 .rating = 200, 153 .rating = 200,
136 .read = nuc900_get_cycles, 154 .read = nuc900_get_cycles,
137 .mask = CLOCKSOURCE_MASK(32), 155 .mask = CLOCKSOURCE_MASK(TDR_SHIFT),
138 .shift = 20, 156 .shift = 10,
139 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 157 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
140}; 158};
141 159
142static void __init nuc900_clocksource_init(unsigned int rate) 160static void __init nuc900_clocksource_init(void)
143{ 161{
144 unsigned int val; 162 unsigned int val;
163 unsigned int rate;
164 struct clk *clk = clk_get(NULL, "timer1");
165
166 BUG_ON(IS_ERR(clk));
167
168 __raw_writel(0x00, REG_TCSR1);
169
170 clk_enable(clk);
171 rate = clk_get_rate(clk) / (PRESCALE + 1);
145 172
146 __raw_writel(0xffffffff, REG_TICR1); 173 __raw_writel(0xffffffff, REG_TICR1);
147 174
148 val = __raw_readl(REG_TCSR1); 175 val = __raw_readl(REG_TCSR1);
149 val |= (COUNTEN | PERIOD); 176 val |= (COUNTEN | PERIOD | PRESCALE);
150 __raw_writel(val, REG_TCSR1); 177 __raw_writel(val, REG_TCSR1);
151 178
152 clocksource_nuc900.mult = 179 clocksource_nuc900.mult =
@@ -156,25 +183,8 @@ static void __init nuc900_clocksource_init(unsigned int rate)
156 183
157static void __init nuc900_timer_init(void) 184static void __init nuc900_timer_init(void)
158{ 185{
159 struct clk *ck_ext = clk_get(NULL, "ext"); 186 nuc900_clocksource_init();
160 unsigned int rate; 187 nuc900_clockevents_init();
161
162 BUG_ON(IS_ERR(ck_ext));
163
164 rate = clk_get_rate(ck_ext);
165 clk_put(ck_ext);
166 rate = rate / (PRESCALE + 0x01);
167
168 /* set a known state */
169 __raw_writel(0x00, REG_TCSR0);
170 __raw_writel(0x00, REG_TCSR1);
171 __raw_writel(RESETINT, REG_TISR);
172 timer0_load = (rate / TICKS_PER_SEC);
173
174 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
175
176 nuc900_clocksource_init(rate);
177 nuc900_clockevents_init(rate);
178} 188}
179 189
180struct sys_timer nuc900_timer = { 190struct sys_timer nuc900_timer = {