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-rw-r--r--arch/arm/mach-vt8500/include/mach/restart.h4
-rw-r--r--arch/arm/mach-vt8500/include/mach/vt8500_irqs.h88
-rw-r--r--arch/arm/mach-vt8500/include/mach/vt8500_regs.h79
-rw-r--r--arch/arm/mach-vt8500/include/mach/wm8505_irqs.h115
-rw-r--r--arch/arm/mach-vt8500/include/mach/wm8505_regs.h78
5 files changed, 2 insertions, 362 deletions
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b787d2a0..738979518acb 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
13 * 13 *
14 */ 14 */
15 15
16void wmt_setup_restart(void); 16void vt8500_setup_restart(void);
17void wmt_restart(char mode, const char *cmd); 17void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee9124711..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* VT8500 Interrupt Sources */
22
23#define IRQ_JPEGENC 0 /* JPEG Encoder */
24#define IRQ_JPEGDEC 1 /* JPEG Decoder */
25 /* Reserved */
26#define IRQ_PATA 3 /* PATA Controller */
27 /* Reserved */
28#define IRQ_DMA 5 /* DMA Controller */
29#define IRQ_EXT0 6 /* External Interrupt 0 */
30#define IRQ_EXT1 7 /* External Interrupt 1 */
31#define IRQ_GE 8 /* Graphic Engine */
32#define IRQ_GOV 9 /* Graphic Overlay Engine */
33#define IRQ_ETHER 10 /* Ethernet MAC */
34#define IRQ_MPEGTS 11 /* Transport Stream Interface */
35#define IRQ_LCDC 12 /* LCD Controller */
36#define IRQ_EXT2 13 /* External Interrupt 2 */
37#define IRQ_EXT3 14 /* External Interrupt 3 */
38#define IRQ_EXT4 15 /* External Interrupt 4 */
39#define IRQ_CIPHER 16 /* Cipher */
40#define IRQ_VPP 17 /* Video Post-Processor */
41#define IRQ_I2C1 18 /* I2C 1 */
42#define IRQ_I2C0 19 /* I2C 0 */
43#define IRQ_SDMMC 20 /* SD/MMC Controller */
44#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */
45#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */
46 /* Reserved */
47#define IRQ_SPI0 24 /* SPI 0 */
48#define IRQ_SPI1 25 /* SPI 1 */
49#define IRQ_SPI2 26 /* SPI 2 */
50#define IRQ_LCDDF 27 /* LCD Data Formatter */
51#define IRQ_NAND 28 /* NAND Flash Controller */
52#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */
53#define IRQ_MS 30 /* MemoryStick Controller */
54#define IRQ_MS_DMA 31 /* MemoryStick Controller DMA */
55#define IRQ_UART0 32 /* UART 0 */
56#define IRQ_UART1 33 /* UART 1 */
57#define IRQ_I2S 34 /* I2S */
58#define IRQ_PCM 35 /* PCM */
59#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */
60#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */
61#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */
62#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */
63#define IRQ_VPU 40 /* Video Processing Unit */
64#define IRQ_VID 41 /* Video Digital Input Interface */
65#define IRQ_AC97 42 /* AC97 Interface */
66#define IRQ_EHCI 43 /* USB */
67#define IRQ_NOR 44 /* NOR Flash Controller */
68#define IRQ_PS2MOUSE 45 /* PS/2 Mouse */
69#define IRQ_PS2KBD 46 /* PS/2 Keyboard */
70#define IRQ_UART2 47 /* UART 2 */
71#define IRQ_RTC 48 /* RTC Interrupt */
72#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */
73#define IRQ_UART3 50 /* UART 3 */
74#define IRQ_ADC 51 /* ADC */
75#define IRQ_EXT5 52 /* External Interrupt 5 */
76#define IRQ_EXT6 53 /* External Interrupt 6 */
77#define IRQ_EXT7 54 /* External Interrupt 7 */
78#define IRQ_CIR 55 /* CIR */
79#define IRQ_DMA0 56 /* DMA Channel 0 */
80#define IRQ_DMA1 57 /* DMA Channel 1 */
81#define IRQ_DMA2 58 /* DMA Channel 2 */
82#define IRQ_DMA3 59 /* DMA Channel 3 */
83#define IRQ_DMA4 60 /* DMA Channel 4 */
84#define IRQ_DMA5 61 /* DMA Channel 5 */
85#define IRQ_DMA6 62 /* DMA Channel 6 */
86#define IRQ_DMA7 63 /* DMA Channel 7 */
87
88#define VT8500_NR_IRQS 64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ecb2383..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * arch/arm/mach-vt8500/include/mach/vt8500_regs.h
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
21#define __ASM_ARM_ARCH_VT8500_REGS_H
22
23/* VT8500 Registers Map */
24
25#define VT8500_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */
26#define VT8500_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */
27
28#define VT8500_DDR_BASE 0xd8000000 /* 1k DDR/DDR2 Memory
29 Controller */
30#define VT8500_DMA_BASE 0xd8001000 /* 1k DMA Controller */
31#define VT8500_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory
32 Controller */
33#define VT8500_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */
34#define VT8500_CIPHER_BASE 0xd8006000 /* 4k Cipher */
35#define VT8500_USB_BASE 0xd8007800 /* 2k USB OTG */
36# define VT8500_EHCI_BASE 0xd8007900 /* EHCI */
37# define VT8500_UHCI_BASE 0xd8007b01 /* UHCI */
38#define VT8500_PATA_BASE 0xd8008000 /* 512 PATA */
39#define VT8500_PS2_BASE 0xd8008800 /* 1k PS/2 */
40#define VT8500_NAND_BASE 0xd8009000 /* 1k NAND Controller */
41#define VT8500_NOR_BASE 0xd8009400 /* 1k NOR Controller */
42#define VT8500_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */
43#define VT8500_MS_BASE 0xd800b000 /* 1k MS/MSPRO Controller */
44#define VT8500_LCDC_BASE 0xd800e400 /* 1k LCD Controller */
45#define VT8500_VPU_BASE 0xd8050000 /* 256 VPU */
46#define VT8500_GOV_BASE 0xd8050300 /* 256 GOV */
47#define VT8500_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */
48#define VT8500_LCDF_BASE 0xd8050900 /* 256 LCD Formatter */
49#define VT8500_VID_BASE 0xd8050a00 /* 256 VID */
50#define VT8500_VPP_BASE 0xd8050b00 /* 256 VPP */
51#define VT8500_TSBK_BASE 0xd80f4000 /* 4k TSBK */
52#define VT8500_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */
53#define VT8500_JPEGENC_BASE 0xd80ff000 /* 4k JPEG Encoder */
54#define VT8500_RTC_BASE 0xd8100000 /* 64k RTC */
55#define VT8500_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */
56#define VT8500_SCC_BASE 0xd8120000 /* 64k System Configuration*/
57#define VT8500_PMC_BASE 0xd8130000 /* 64k PMC Configuration */
58#define VT8500_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/
59#define VT8500_UART0_BASE 0xd8200000 /* 64k UART 0 */
60#define VT8500_UART2_BASE 0xd8210000 /* 64k UART 2 */
61#define VT8500_PWM_BASE 0xd8220000 /* 64k PWM Configuration */
62#define VT8500_SPI0_BASE 0xd8240000 /* 64k SPI 0 */
63#define VT8500_SPI1_BASE 0xd8250000 /* 64k SPI 1 */
64#define VT8500_CIR_BASE 0xd8270000 /* 64k CIR */
65#define VT8500_I2C0_BASE 0xd8280000 /* 64k I2C 0 */
66#define VT8500_AC97_BASE 0xd8290000 /* 64k AC97 */
67#define VT8500_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */
68#define VT8500_UART1_BASE 0xd82b0000 /* 64k UART 1 */
69#define VT8500_UART3_BASE 0xd82c0000 /* 64k UART 3 */
70#define VT8500_PCM_BASE 0xd82d0000 /* 64k PCM */
71#define VT8500_I2C1_BASE 0xd8320000 /* 64k I2C 1 */
72#define VT8500_I2S_BASE 0xd8330000 /* 64k I2S */
73#define VT8500_ADC_BASE 0xd8340000 /* 64k ADC */
74
75#define VT8500_REGS_END_PHYS 0xd834ffff /* End of MMIO registers */
76#define VT8500_REGS_LENGTH (VT8500_REGS_END_PHYS \
77 - VT8500_REGS_START_PHYS + 1)
78
79#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627ac753..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* WM8505 Interrupt Sources */
22
23#define IRQ_UHCI 0 /* UHC FS (UHCI?) */
24#define IRQ_EHCI 1 /* UHC HS */
25#define IRQ_UDCDMA 2 /* UDC DMA */
26 /* Reserved */
27#define IRQ_PS2MOUSE 4 /* PS/2 Mouse */
28#define IRQ_UDC 5 /* UDC */
29#define IRQ_EXT0 6 /* External Interrupt 0 */
30#define IRQ_EXT1 7 /* External Interrupt 1 */
31#define IRQ_KEYPAD 8 /* Keypad */
32#define IRQ_DMA 9 /* DMA Controller */
33#define IRQ_ETHER 10 /* Ethernet MAC */
34 /* Reserved */
35 /* Reserved */
36#define IRQ_EXT2 13 /* External Interrupt 2 */
37#define IRQ_EXT3 14 /* External Interrupt 3 */
38#define IRQ_EXT4 15 /* External Interrupt 4 */
39#define IRQ_APB 16 /* APB Bridge */
40#define IRQ_DMA0 17 /* DMA Channel 0 */
41#define IRQ_I2C1 18 /* I2C 1 */
42#define IRQ_I2C0 19 /* I2C 0 */
43#define IRQ_SDMMC 20 /* SD/MMC Controller */
44#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */
45#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */
46#define IRQ_PS2KBD 23 /* PS/2 Keyboard */
47#define IRQ_SPI0 24 /* SPI 0 */
48#define IRQ_SPI1 25 /* SPI 1 */
49#define IRQ_SPI2 26 /* SPI 2 */
50#define IRQ_DMA1 27 /* DMA Channel 1 */
51#define IRQ_NAND 28 /* NAND Flash Controller */
52#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */
53#define IRQ_UART5 30 /* UART 5 */
54#define IRQ_UART4 31 /* UART 4 */
55#define IRQ_UART0 32 /* UART 0 */
56#define IRQ_UART1 33 /* UART 1 */
57#define IRQ_DMA2 34 /* DMA Channel 2 */
58#define IRQ_I2S 35 /* I2S */
59#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */
60#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */
61#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */
62#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */
63#define IRQ_DMA3 40 /* DMA Channel 3 */
64#define IRQ_DMA4 41 /* DMA Channel 4 */
65#define IRQ_AC97 42 /* AC97 Interface */
66 /* Reserved */
67#define IRQ_NOR 44 /* NOR Flash Controller */
68#define IRQ_DMA5 45 /* DMA Channel 5 */
69#define IRQ_DMA6 46 /* DMA Channel 6 */
70#define IRQ_UART2 47 /* UART 2 */
71#define IRQ_RTC 48 /* RTC Interrupt */
72#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */
73#define IRQ_UART3 50 /* UART 3 */
74#define IRQ_DMA7 51 /* DMA Channel 7 */
75#define IRQ_EXT5 52 /* External Interrupt 5 */
76#define IRQ_EXT6 53 /* External Interrupt 6 */
77#define IRQ_EXT7 54 /* External Interrupt 7 */
78#define IRQ_CIR 55 /* CIR */
79#define IRQ_SIC0 56 /* SIC IRQ0 */
80#define IRQ_SIC1 57 /* SIC IRQ1 */
81#define IRQ_SIC2 58 /* SIC IRQ2 */
82#define IRQ_SIC3 59 /* SIC IRQ3 */
83#define IRQ_SIC4 60 /* SIC IRQ4 */
84#define IRQ_SIC5 61 /* SIC IRQ5 */
85#define IRQ_SIC6 62 /* SIC IRQ6 */
86#define IRQ_SIC7 63 /* SIC IRQ7 */
87 /* Reserved */
88#define IRQ_JPEGDEC 65 /* JPEG Decoder */
89#define IRQ_SAE 66 /* SAE (?) */
90 /* Reserved */
91#define IRQ_VPU 79 /* Video Processing Unit */
92#define IRQ_VPP 80 /* Video Post-Processor */
93#define IRQ_VID 81 /* Video Digital Input Interface */
94#define IRQ_SPU 82 /* SPU (?) */
95#define IRQ_PIP 83 /* PIP Error */
96#define IRQ_GE 84 /* Graphic Engine */
97#define IRQ_GOV 85 /* Graphic Overlay Engine */
98#define IRQ_DVO 86 /* Digital Video Output */
99 /* Reserved */
100#define IRQ_DMA8 92 /* DMA Channel 8 */
101#define IRQ_DMA9 93 /* DMA Channel 9 */
102#define IRQ_DMA10 94 /* DMA Channel 10 */
103#define IRQ_DMA11 95 /* DMA Channel 11 */
104#define IRQ_DMA12 96 /* DMA Channel 12 */
105#define IRQ_DMA13 97 /* DMA Channel 13 */
106#define IRQ_DMA14 98 /* DMA Channel 14 */
107#define IRQ_DMA15 99 /* DMA Channel 15 */
108 /* Reserved */
109#define IRQ_GOVW 111 /* GOVW (?) */
110#define IRQ_GOVRSDSCD 112 /* GOVR SDSCD (?) */
111#define IRQ_GOVRSDMIF 113 /* GOVR SDMIF (?) */
112#define IRQ_GOVRHDSCD 114 /* GOVR HDSCD (?) */
113#define IRQ_GOVRHDMIF 115 /* GOVR HDMIF (?) */
114
115#define WM8505_NR_IRQS 116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df1550941efb..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * arch/arm/mach-vt8500/include/mach/wm8505_regs.h
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
21#define __ASM_ARM_ARCH_WM8505_REGS_H
22
23/* WM8505 Registers Map */
24
25#define WM8505_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */
26#define WM8505_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */
27
28#define WM8505_DDR_BASE 0xd8000400 /* 1k DDR/DDR2 Memory
29 Controller */
30#define WM8505_DMA_BASE 0xd8001800 /* 1k DMA Controller */
31#define WM8505_VDMA_BASE 0xd8001c00 /* 1k VDMA */
32#define WM8505_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory
33 Controller */
34#define WM8505_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */
35#define WM8505_CIPHER_BASE 0xd8006000 /* 4k Cipher */
36#define WM8505_USB_BASE 0xd8007000 /* 2k USB 2.0 Host */
37# define WM8505_EHCI_BASE 0xd8007100 /* EHCI */
38# define WM8505_UHCI_BASE 0xd8007301 /* UHCI */
39#define WM8505_PS2_BASE 0xd8008800 /* 1k PS/2 */
40#define WM8505_NAND_BASE 0xd8009000 /* 1k NAND Controller */
41#define WM8505_NOR_BASE 0xd8009400 /* 1k NOR Controller */
42#define WM8505_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */
43#define WM8505_VPU_BASE 0xd8050000 /* 256 VPU */
44#define WM8505_GOV_BASE 0xd8050300 /* 256 GOV */
45#define WM8505_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */
46#define WM8505_GOVR_BASE 0xd8050800 /* 512 GOVR (frambuffer) */
47#define WM8505_VID_BASE 0xd8050a00 /* 256 VID */
48#define WM8505_SCL_BASE 0xd8050d00 /* 256 SCL */
49#define WM8505_VPP_BASE 0xd8050f00 /* 256 VPP */
50#define WM8505_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */
51#define WM8505_RTC_BASE 0xd8100000 /* 64k RTC */
52#define WM8505_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */
53#define WM8505_SCC_BASE 0xd8120000 /* 64k System Configuration*/
54#define WM8505_PMC_BASE 0xd8130000 /* 64k PMC Configuration */
55#define WM8505_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/
56#define WM8505_SIC_BASE 0xd8150000 /* 64k Secondary IC */
57#define WM8505_UART0_BASE 0xd8200000 /* 64k UART 0 */
58#define WM8505_UART2_BASE 0xd8210000 /* 64k UART 2 */
59#define WM8505_PWM_BASE 0xd8220000 /* 64k PWM Configuration */
60#define WM8505_SPI0_BASE 0xd8240000 /* 64k SPI 0 */
61#define WM8505_SPI1_BASE 0xd8250000 /* 64k SPI 1 */
62#define WM8505_KEYPAD_BASE 0xd8260000 /* 64k Keypad control */
63#define WM8505_CIR_BASE 0xd8270000 /* 64k CIR */
64#define WM8505_I2C0_BASE 0xd8280000 /* 64k I2C 0 */
65#define WM8505_AC97_BASE 0xd8290000 /* 64k AC97 */
66#define WM8505_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */
67#define WM8505_UART1_BASE 0xd82b0000 /* 64k UART 1 */
68#define WM8505_UART3_BASE 0xd82c0000 /* 64k UART 3 */
69#define WM8505_I2C1_BASE 0xd8320000 /* 64k I2C 1 */
70#define WM8505_I2S_BASE 0xd8330000 /* 64k I2S */
71#define WM8505_UART4_BASE 0xd8370000 /* 64k UART 4 */
72#define WM8505_UART5_BASE 0xd8380000 /* 64k UART 5 */
73
74#define WM8505_REGS_END_PHYS 0xd838ffff /* End of MMIO registers */
75#define WM8505_REGS_LENGTH (WM8505_REGS_END_PHYS \
76 - WM8505_REGS_START_PHYS + 1)
77
78#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 00:18:42 -0500