diff options
Diffstat (limited to 'arch/arm/mach-vexpress/ct-ca9x4.c')
-rw-r--r-- | arch/arm/mach-vexpress/ct-ca9x4.c | 107 |
1 files changed, 44 insertions, 63 deletions
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index e9bccc5230c9..ebc22e759325 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
@@ -10,19 +10,17 @@ | |||
10 | #include <linux/amba/clcd.h> | 10 | #include <linux/amba/clcd.h> |
11 | #include <linux/clkdev.h> | 11 | #include <linux/clkdev.h> |
12 | 12 | ||
13 | #include <asm/pgtable.h> | ||
14 | #include <asm/hardware/arm_timer.h> | 13 | #include <asm/hardware/arm_timer.h> |
15 | #include <asm/hardware/cache-l2x0.h> | 14 | #include <asm/hardware/cache-l2x0.h> |
16 | #include <asm/hardware/gic.h> | 15 | #include <asm/hardware/gic.h> |
17 | #include <asm/mach-types.h> | ||
18 | #include <asm/pmu.h> | 16 | #include <asm/pmu.h> |
17 | #include <asm/smp_scu.h> | ||
19 | #include <asm/smp_twd.h> | 18 | #include <asm/smp_twd.h> |
20 | 19 | ||
21 | #include <mach/ct-ca9x4.h> | 20 | #include <mach/ct-ca9x4.h> |
22 | 21 | ||
23 | #include <asm/hardware/timer-sp.h> | 22 | #include <asm/hardware/timer-sp.h> |
24 | 23 | ||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
27 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
28 | 26 | ||
@@ -30,6 +28,8 @@ | |||
30 | 28 | ||
31 | #include <mach/motherboard.h> | 29 | #include <mach/motherboard.h> |
32 | 30 | ||
31 | #include <plat/clcd.h> | ||
32 | |||
33 | #define V2M_PA_CS7 0x10000000 | 33 | #define V2M_PA_CS7 0x10000000 |
34 | 34 | ||
35 | static struct map_desc ct_ca9x4_io_desc[] __initdata = { | 35 | static struct map_desc ct_ca9x4_io_desc[] __initdata = { |
@@ -56,7 +56,7 @@ static void __init ct_ca9x4_map_io(void) | |||
56 | #ifdef CONFIG_LOCAL_TIMERS | 56 | #ifdef CONFIG_LOCAL_TIMERS |
57 | twd_base = MMIO_P2V(A9_MPCORE_TWD); | 57 | twd_base = MMIO_P2V(A9_MPCORE_TWD); |
58 | #endif | 58 | #endif |
59 | v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); | 59 | iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); |
60 | } | 60 | } |
61 | 61 | ||
62 | static void __init ct_ca9x4_init_irq(void) | 62 | static void __init ct_ca9x4_init_irq(void) |
@@ -80,29 +80,6 @@ static struct sys_timer ct_ca9x4_timer = { | |||
80 | }; | 80 | }; |
81 | #endif | 81 | #endif |
82 | 82 | ||
83 | static struct clcd_panel xvga_panel = { | ||
84 | .mode = { | ||
85 | .name = "XVGA", | ||
86 | .refresh = 60, | ||
87 | .xres = 1024, | ||
88 | .yres = 768, | ||
89 | .pixclock = 15384, | ||
90 | .left_margin = 168, | ||
91 | .right_margin = 8, | ||
92 | .upper_margin = 29, | ||
93 | .lower_margin = 3, | ||
94 | .hsync_len = 144, | ||
95 | .vsync_len = 6, | ||
96 | .sync = 0, | ||
97 | .vmode = FB_VMODE_NONINTERLACED, | ||
98 | }, | ||
99 | .width = -1, | ||
100 | .height = -1, | ||
101 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
102 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
103 | .bpp = 16, | ||
104 | }; | ||
105 | |||
106 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) | 83 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) |
107 | { | 84 | { |
108 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); | 85 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); |
@@ -112,42 +89,23 @@ static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) | |||
112 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) | 89 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) |
113 | { | 90 | { |
114 | unsigned long framesize = 1024 * 768 * 2; | 91 | unsigned long framesize = 1024 * 768 * 2; |
115 | dma_addr_t dma; | ||
116 | 92 | ||
117 | fb->panel = &xvga_panel; | 93 | fb->panel = versatile_clcd_get_panel("XVGA"); |
94 | if (!fb->panel) | ||
95 | return -EINVAL; | ||
118 | 96 | ||
119 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | 97 | return versatile_clcd_setup_dma(fb, framesize); |
120 | &dma, GFP_KERNEL); | ||
121 | if (!fb->fb.screen_base) { | ||
122 | printk(KERN_ERR "CLCD: unable to map frame buffer\n"); | ||
123 | return -ENOMEM; | ||
124 | } | ||
125 | fb->fb.fix.smem_start = dma; | ||
126 | fb->fb.fix.smem_len = framesize; | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
132 | { | ||
133 | return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, | ||
134 | fb->fb.fix.smem_start, fb->fb.fix.smem_len); | ||
135 | } | ||
136 | |||
137 | static void ct_ca9x4_clcd_remove(struct clcd_fb *fb) | ||
138 | { | ||
139 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | ||
140 | fb->fb.screen_base, fb->fb.fix.smem_start); | ||
141 | } | 98 | } |
142 | 99 | ||
143 | static struct clcd_board ct_ca9x4_clcd_data = { | 100 | static struct clcd_board ct_ca9x4_clcd_data = { |
144 | .name = "CT-CA9X4", | 101 | .name = "CT-CA9X4", |
102 | .caps = CLCD_CAP_5551 | CLCD_CAP_565, | ||
145 | .check = clcdfb_check, | 103 | .check = clcdfb_check, |
146 | .decode = clcdfb_decode, | 104 | .decode = clcdfb_decode, |
147 | .enable = ct_ca9x4_clcd_enable, | 105 | .enable = ct_ca9x4_clcd_enable, |
148 | .setup = ct_ca9x4_clcd_setup, | 106 | .setup = ct_ca9x4_clcd_setup, |
149 | .mmap = ct_ca9x4_clcd_mmap, | 107 | .mmap = versatile_clcd_mmap_dma, |
150 | .remove = ct_ca9x4_clcd_remove, | 108 | .remove = versatile_clcd_remove_dma, |
151 | }; | 109 | }; |
152 | 110 | ||
153 | static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); | 111 | static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); |
@@ -220,6 +178,11 @@ static struct platform_device pmu_device = { | |||
220 | .resource = pmu_resources, | 178 | .resource = pmu_resources, |
221 | }; | 179 | }; |
222 | 180 | ||
181 | static void __init ct_ca9x4_init_early(void) | ||
182 | { | ||
183 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
184 | } | ||
185 | |||
223 | static void __init ct_ca9x4_init(void) | 186 | static void __init ct_ca9x4_init(void) |
224 | { | 187 | { |
225 | int i; | 188 | int i; |
@@ -234,22 +197,40 @@ static void __init ct_ca9x4_init(void) | |||
234 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); | 197 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); |
235 | #endif | 198 | #endif |
236 | 199 | ||
237 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
238 | |||
239 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) | 200 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) |
240 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); | 201 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); |
241 | 202 | ||
242 | platform_device_register(&pmu_device); | 203 | platform_device_register(&pmu_device); |
243 | } | 204 | } |
244 | 205 | ||
245 | MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") | 206 | #ifdef CONFIG_SMP |
246 | .boot_params = PLAT_PHYS_OFFSET + 0x00000100, | 207 | static void ct_ca9x4_init_cpu_map(void) |
208 | { | ||
209 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); | ||
210 | |||
211 | for (i = 0; i < ncores; ++i) | ||
212 | set_cpu_possible(i, true); | ||
213 | } | ||
214 | |||
215 | static void ct_ca9x4_smp_enable(unsigned int max_cpus) | ||
216 | { | ||
217 | int i; | ||
218 | for (i = 0; i < max_cpus; i++) | ||
219 | set_cpu_present(i, true); | ||
220 | |||
221 | scu_enable(MMIO_P2V(A9_MPCORE_SCU)); | ||
222 | } | ||
223 | #endif | ||
224 | |||
225 | struct ct_desc ct_ca9x4_desc __initdata = { | ||
226 | .id = V2M_CT_ID_CA9, | ||
227 | .name = "CA9x4", | ||
247 | .map_io = ct_ca9x4_map_io, | 228 | .map_io = ct_ca9x4_map_io, |
229 | .init_early = ct_ca9x4_init_early, | ||
248 | .init_irq = ct_ca9x4_init_irq, | 230 | .init_irq = ct_ca9x4_init_irq, |
249 | #if 0 | 231 | .init_tile = ct_ca9x4_init, |
250 | .timer = &ct_ca9x4_timer, | 232 | #ifdef CONFIG_SMP |
251 | #else | 233 | .init_cpu_map = ct_ca9x4_init_cpu_map, |
252 | .timer = &v2m_timer, | 234 | .smp_enable = ct_ca9x4_smp_enable, |
253 | #endif | 235 | #endif |
254 | .init_machine = ct_ca9x4_init, | 236 | }; |
255 | MACHINE_END | ||