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-rw-r--r--arch/arm/mach-versatile/core.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 6bbd74e950ab..6f5fb466a273 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -66,12 +66,6 @@
66#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) 66#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
67#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) 67#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
68 68
69static struct fpga_irq_data sic_irq = {
70 .base = VA_SIC_BASE,
71 .irq_start = IRQ_SIC_START,
72 .chip.name = "SIC",
73};
74
75#if 1 69#if 1
76#define IRQ_MMCI0A IRQ_VICSOURCE22 70#define IRQ_MMCI0A IRQ_VICSOURCE22
77#define IRQ_AACI IRQ_VICSOURCE24 71#define IRQ_AACI IRQ_VICSOURCE24
@@ -105,8 +99,11 @@ void __init versatile_init_irq(void)
105 99
106 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 100 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
107 101
108 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq); 102 np = of_find_matching_node_by_address(NULL, sic_of_match,
109 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START); 103 VERSATILE_SIC_BASE);
104
105 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
106 IRQ_VICSOURCE31, ~PIC_MASK, np);
110 107
111 /* 108 /*
112 * Interrupts on secondary controller from 0 to 8 are routed to 109 * Interrupts on secondary controller from 0 to 8 are routed to